[net,0/7] Xilinx axienet fixes

Message

Robert Hancock Jan. 11, 2022, 9:13 p.m. UTC

Various fixes for the Xilinx AXI Ethernet driver.

Robert Hancock (7):
  net: axienet: Reset core before accessing MAC and wait for core ready
  net: axienet: add missing memory barriers
  net: axienet: limit minimum TX ring size
  net: axienet: Fix TX ring slot available check
  net: axienet: fix number of TX ring slots for available check
  net: axienet: fix for TX busy handling
  net: axienet: increase default TX ring size to 128

 .../net/ethernet/xilinx/xilinx_axienet_main.c | 134 +++++++++++-------
 1 file changed, 83 insertions(+), 51 deletions(-)