Message ID | 20230411090359.5134-1-hkelam@marvell.com (mailing list archive) |
---|---|
Headers | show |
Series | octeontx2-pf: HTB offload support | expand |
On Tue, Apr 11, 2023 at 02:33:53PM +0530, Hariprasad Kelam wrote: > octeontx2 silicon and CN10K transmit interface consists of five > transmit levels starting from MDQ, TL4 to TL1. Once packets are > submitted to MDQ, hardware picks all active MDQs using strict > priority, and MDQs having the same priority level are chosen using > round robin. Each packet will traverse MDQ, TL4 to TL1 levels. > Each level contains an array of queues to support scheduling and > shaping. > > As HTB supports classful queuing mechanism by supporting rate and > ceil and allow the user to control the absolute bandwidth to > particular classes of traffic the same can be achieved by > configuring shapers and schedulers on different transmit levels. > > This series of patches adds support for HTB offload, > > Patch1: Allow strict priority parameter in HTB offload mode. > > Patch2: Rename existing total tx queues for better readability > > Patch3: defines APIs such that the driver can dynamically initialize/ > deinitialize the send queues. > > Patch4: Refactors transmit alloc/free calls as preparation for QOS > offload code. > > Patch5: Adds actual HTB offload support. > > Patch6: Add documentation about htb offload flow in driver > > Hariprasad Kelam (3): > octeontx2-pf: Rename tot_tx_queues to non_qos_queues > octeontx2-pf: Refactor schedular queue alloc/free calls > docs: octeontx2: Add Documentation for QOS > > Naveen Mamindlapalli (2): > sch_htb: Allow HTB priority parameter in offload mode > octeontx2-pf: Add support for HTB offload > > Subbaraya Sundeep (1): > octeontx2-pf: qos send queues management > ----- > v1 -> v2 : > ensure other drivers won't affect by allowing 'prio' > a parameter in htb offload mode. > > v2 -> v3 : > 1. discard patch supporting devlink to configure TL1 round > robin priority > 2. replace NL_SET_ERR_MSG with NL_SET_ERR_MSG_MOD > 3. use max3 instead of using max couple of times and use a better > naming convention in send queue management code. > > v3 -> v4: > 1. fix sparse warnings. > 2. release mutex lock in error conditions. > > v4 -> v5: > 1. fix pahole reported issues > 2. add documentation for htb offload flow. > > v5 -> v6: > 1. fix synchronization issues w.r.t hlist accessing > from ndo_select_queue with rcu lock. > 2. initialize qos related resources in device init. > > v6 -> v7: > 1. fix erros reported by sparse and clang > > v7 -> v8: > 1. cover letter header is malformed in last version. > correct the cover letter > v8 -> v9: > 1. fix issues reported by smatch Thanks. I checked and all issues I've reported are resolved.
On Tue, 11 Apr 2023 14:33:53 +0530 Hariprasad Kelam wrote: > octeontx2 silicon and CN10K transmit interface consists of five > transmit levels starting from MDQ, TL4 to TL1. Once packets are > submitted to MDQ, hardware picks all active MDQs using strict > priority, and MDQs having the same priority level are chosen using > round robin. Each packet will traverse MDQ, TL4 to TL1 levels. > Each level contains an array of queues to support scheduling and > shaping. Looks like Jake's comments from v7 apply. Jake, sorry for not cleaning up patchwork the bad series name has fooled the bot.
On Wed, 2023-04-12 at 18:27 -0700, Jakub Kicinski wrote: > On Tue, 11 Apr 2023 14:33:53 +0530 Hariprasad Kelam wrote: > > octeontx2 silicon and CN10K transmit interface consists of five > > transmit levels starting from MDQ, TL4 to TL1. Once packets are > > submitted to MDQ, hardware picks all active MDQs using strict > > priority, and MDQs having the same priority level are chosen using > > round robin. Each packet will traverse MDQ, TL4 to TL1 levels. > > Each level contains an array of queues to support scheduling and > > shaping. > > > Looks like Jake's comments from v7 apply. Just to be more verbose, the above means clarifying the commit message for patch 4/6 and try factor into separate helpers some code of function __otx2_qos_txschq_cfg() in patch 6/6. Thanks, Paolo
> On Wed, 2023-04-12 at 18:27 -0700, Jakub Kicinski wrote: > > On Tue, 11 Apr 2023 14:33:53 +0530 Hariprasad Kelam wrote: > > > octeontx2 silicon and CN10K transmit interface consists of five > > > transmit levels starting from MDQ, TL4 to TL1. Once packets are > > > submitted to MDQ, hardware picks all active MDQs using strict > > > priority, and MDQs having the same priority level are chosen using > > > round robin. Each packet will traverse MDQ, TL4 to TL1 levels. > > > Each level contains an array of queues to support scheduling and > > > shaping. > > > > > > Looks like Jake's comments from v7 apply. > > Just to be more verbose, the above means clarifying the commit message for > patch 4/6 and try factor into separate helpers some code of function > __otx2_qos_txschq_cfg() in patch 6/6. > ACK, will address in next version. Thanks, Hariprasad k > Thanks, > > Paolo