[net,0/3] net: phy: mscc: support VSC8501

Message

David Epping May 20, 2023, 4:06 p.m. UTC

Hello,

this series of patches adds support for the VSC8501 Ethernet PHY and
fixes support for the VSC8502 PHY in RGMII mode (see below for
discussion).

The first patch simply adds the VSC8502 to the MODULE_DEVICE_TABLE,
where I guess it was unintentionally missing. I have no hardware to
test my change.

The second patch adds the VSC8501 PHY with exactly the same driver
implementation as the existing VSC8502. Note that for at least RGMII
mode this patch is not sufficient to operate the PHY, but likely the
existing code was not sufficient for VSC8502, either.

The third patch fixes RGMII mode operation for the VSC8501 (I have
tested this on hardware) and very likely also the VSC8502, which share
the same description of relevant registers in the datasheet.
https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/VSC8501-03_Datasheet_60001741A.PDF
https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/VSC8502-03_Datasheet_60001742B.pdf
Table 4-42 "RGMII CONTROL, ADDRESS 20E2 (0X14)" Bit 11 for each of
them.

By default the RX_CLK is disabled in both PHYs. This results in no
received packets being handed to the MAC. The patch enables this
clock.
Since I can only test RGMII mode, and the register is called RGMII,
my patch is limited to the RGMII mode. However, according to
Microchip support (case number 01268776) this applies to all modes
using the RX_CLK (which is all modes?).
Since the VSC8502 shares the same description, this would however mean
the existing code for VSC8502 could have never worked.
Is that possible? Has someone used VSC8502 successfully?

Other PHYs sharing the same basic code, like VSC8530/31/40/41 don't
have the clock disabled and the bit 11 is reserved for them.
Hence the check for PHY ID.

Should the uncertainty about GMII and MII modes be a source code
comment? Or in the commit message? Or not mentioned at all?

Thanks for your feedback,
David

David Epping (3):
  net: phy: mscc: add VSC8502 to MODULE_DEVICE_TABLE
  net: phy: mscc: add support for VSC8501
  net: phy: mscc: enable VSC8501/2 RGMII RX clock

 drivers/net/phy/mscc/mscc.h      |  2 ++
 drivers/net/phy/mscc/mscc_main.c | 50 ++++++++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)

Comments

Vladimir Oltean May 21, 2023, 1:33 p.m. UTC | #1

On Sat, May 20, 2023 at 06:06:00PM +0200, David Epping wrote:
> Since I can only test RGMII mode, and the register is called RGMII,
> my patch is limited to the RGMII mode. However, according to
> Microchip support (case number 01268776) this applies to all modes
> using the RX_CLK (which is all modes?).

I logged into my Microchip support account, but it looks like I can only
view cases which are mine. If they say that bit 11 applies to all PHY
modes where the PHY drives RX_CLK, that would mean MII, GMII and RGMII.

> Since the VSC8502 shares the same description, this would however mean
> the existing code for VSC8502 could have never worked.
> Is that possible? Has someone used VSC8502 successfully?

Yup (with U-Boot pre-initialization though). Thanks for the investigation.

> Other PHYs sharing the same basic code, like VSC8530/31/40/41 don't
> have the clock disabled and the bit 11 is reserved for them.
> Hence the check for PHY ID.
> 
> Should the uncertainty about GMII and MII modes be a source code
> comment? Or in the commit message? Or not mentioned at all?

I think we'd be better off moving the vsc85xx_rgmii_enable_rx_clk() call
outside the "if phy_interface_mode_is_rgmii(phydev->interface)" block,
if that's what Microchip support seems to suggest.