| Message ID | 20230529080246.82953-1-alexis.lothore@bootlin.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | net: dsa: mv88e6xxx: add 88E6361 support | expand |
Hello: This series was applied to netdev/net-next.git (main) by Jakub Kicinski <kuba@kernel.org>: On Mon, 29 May 2023 10:02:39 +0200 you wrote: > This series brings initial support for Marvell 88E6361 switch. > > MV88E6361 is a 8 ports switch with 5 integrated Gigabit PHYs and 3 > 2.5Gigabit SerDes interfaces. It is in fact a new variant in the > 88E639X/88E6193X/88E6191X family with a subset of existing features: > - port 0: MII, RMII, RGMII, 1000BaseX, 2500BaseX > - port 3 to 7: triple speed internal phys > - port 9 and 10: 1000BaseX, 25000BaseX > > [...] Here is the summary with links: - [net-next,v4,1/7] dt-bindings: net: dsa: marvell: add MV88E6361 switch to compatibility list https://git.kernel.org/netdev/net-next/c/9229a9483d80 - [net-next,v4,2/7] net: dsa: mv88e6xxx: pass directly chip structure to mv88e6xxx_phy_is_internal https://git.kernel.org/netdev/net-next/c/ca345931907f - [net-next,v4,3/7] net: dsa: mv88e6xxx: use mv88e6xxx_phy_is_internal in mv88e6xxx_port_ppu_updates https://git.kernel.org/netdev/net-next/c/7a2dd00be869 - [net-next,v4,4/7] net: dsa: mv88e6xxx: add field to specify internal phys layout https://git.kernel.org/netdev/net-next/c/3ba89b28adb2 - [net-next,v4,5/7] net: dsa: mv88e6xxx: fix 88E6393X family internal phys layout https://git.kernel.org/netdev/net-next/c/2f93493970df - [net-next,v4,6/7] net: dsa: mv88e6xxx: pass mv88e6xxx_chip structure to port_max_speed_mode https://git.kernel.org/netdev/net-next/c/18e1b7422dff - [net-next,v4,7/7] net: dsa: mv88e6xxx: enable support for 88E6361 switch https://git.kernel.org/netdev/net-next/c/12899f299803 You are awesome, thank you!
This series brings initial support for Marvell 88E6361 switch. MV88E6361 is a 8 ports switch with 5 integrated Gigabit PHYs and 3 2.5Gigabit SerDes interfaces. It is in fact a new variant in the 88E639X/88E6193X/88E6191X family with a subset of existing features: - port 0: MII, RMII, RGMII, 1000BaseX, 2500BaseX - port 3 to 7: triple speed internal phys - port 9 and 10: 1000BaseX, 25000BaseX Since said family is already well supported in mv88e6xxx driver, adding initial support for this new switch mostly consists in finding the ID exposed in its identification register, adding a proper description in switch description tables in mv88e6xxx driver, and enforcing 88E6361 specificities in mv88e6393x_XXX methods. - first 4 commits introduce an internal phy offset field for switches which have internal phys but not starting from port 0 - 5th commit is a fix on existing switches based on first commits - 6th commit is a slight modification to prepare 886361 support - last commit introduces 88E6361 support in 88E6393X family This initial support has been tested with two samples of a custom board with the following hardware configuration: - a main CPU connected to MV88E6361 using port 0 as CPU port - port 9 wired to a SFP cage - port 10 wired to a G.Hn transceiver The following setup was used: PC <-ethernet-> (copper SFP) - Board 1 - (G.hn) <-phone line(RJ11)-> (G.hn) Board 2 The unit 1 has been configured to bridge SFP port and G.hn port together, which allowed to successfully ping Board 2 from PC. Changes since v3: - fix SoB - reorder switch id list Changes since v2: - add Reviewed-By tags for untouched patches - remove whitespace - reorganized some conditions to avoid weird line split Changes since v1: - rework mv88e6xxx_port_ppu_updates to use internal helper - add internal phys offset field to manage switches which do not have internal PHYs right on first ports - fix 88E639X/88E6193X/88E6191X internal phy layout - enforce 88E6361 features in mv88e6393x_port_set_speed_duplex - enforce 88E6361 features in mv88e6393x_port_max_speed_mode - enforce 88E6361 features in mv88e6393x_phylink_get_caps - add Reviewed-By and Acked-By on untouched patch Alexis Lothoré (7): dt-bindings: net: dsa: marvell: add MV88E6361 switch to compatibility list net: dsa: mv88e6xxx: pass directly chip structure to mv88e6xxx_phy_is_internal net: dsa: mv88e6xxx: use mv88e6xxx_phy_is_internal in mv88e6xxx_port_ppu_updates net: dsa: mv88e6xxx: add field to specify internal phys layout net: dsa: mv88e6xxx: fix 88E6393X family internal phys layout net: dsa: mv88e6xxx: pass mv88e6xxx_chip structure to port_max_speed_mode net: dsa: mv88e6xxx: enable support for 88E6361 switch .../devicetree/bindings/net/dsa/marvell.txt | 2 +- drivers/net/dsa/mv88e6xxx/chip.c | 69 ++++++++++++++----- drivers/net/dsa/mv88e6xxx/chip.h | 11 ++- drivers/net/dsa/mv88e6xxx/global2.c | 5 +- drivers/net/dsa/mv88e6xxx/port.c | 26 +++++-- drivers/net/dsa/mv88e6xxx/port.h | 13 ++-- 6 files changed, 94 insertions(+), 32 deletions(-)