| Message ID | 20231220155518.15692-1-kabel@kernel.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | Realtek RTL822x PHY rework to c45 and SerDes interface switching | expand |
On 20.12.2023 16:55, Marek Behún wrote: > Hi, > > this series reworks the realtek PHY driver's support for rtl822x > 2.5G transceivers: > > - First I change the driver so that the high level driver methods > only use clause 45 register accesses (the only clause 22 accesses > are left when accessing c45 registers indirectly, if the MDIO bus > does not support clause 45 accesses). > The driver starts using the genphy_c45_* methods. > > At this point the driver is ready to be used on a MDIO bus capable > of only clause 45 accesses, but will still work on clause 22 only > MDIO bus. > > - I then add support for SerDes mode switching between 2500base-x > and sgmii, based on autonegotiated copper speed. > > All this is done so that we can support another 2.5G copper SFP > module, which is enabled by the last patch. > Has been verified that the RTL8125-integrated PHY's still work properly with this patch set?
On Wed, 20 Dec 2023 17:20:07 +0100 Heiner Kallweit <hkallweit1@gmail.com> wrote: > On 20.12.2023 16:55, Marek Behún wrote: > > Hi, > > > > this series reworks the realtek PHY driver's support for rtl822x > > 2.5G transceivers: > > > > - First I change the driver so that the high level driver methods > > only use clause 45 register accesses (the only clause 22 accesses > > are left when accessing c45 registers indirectly, if the MDIO bus > > does not support clause 45 accesses). > > The driver starts using the genphy_c45_* methods. > > > > At this point the driver is ready to be used on a MDIO bus capable > > of only clause 45 accesses, but will still work on clause 22 only > > MDIO bus. > > > > - I then add support for SerDes mode switching between 2500base-x > > and sgmii, based on autonegotiated copper speed. > > > > All this is done so that we can support another 2.5G copper SFP > > module, which is enabled by the last patch. > > > > Has been verified that the RTL8125-integrated PHY's still work > properly with this patch set? > Hi Heiner, no, I wanted to send you an email to test this. I do not have the controllers with integrates PHYs. Can you test this? Also do you have a controller where the rtlgen driver is used but it only supports 1gbps ? I.e. where the PHY ID is RTL_GENERIC_PHYID (0x001cc800). I am asking because I am told that it also is clause 45, so the drivers can potentially be merged completely (the rtl822x_ functions can be merged with rtlgen_ functions and everything rewritten to clause 45, and gentphy_c45_ functions can be used). Marek
On 20.12.2023 17:25, Marek Behún wrote: > On Wed, 20 Dec 2023 17:20:07 +0100 > Heiner Kallweit <hkallweit1@gmail.com> wrote: > >> On 20.12.2023 16:55, Marek Behún wrote: >>> Hi, >>> >>> this series reworks the realtek PHY driver's support for rtl822x >>> 2.5G transceivers: >>> >>> - First I change the driver so that the high level driver methods >>> only use clause 45 register accesses (the only clause 22 accesses >>> are left when accessing c45 registers indirectly, if the MDIO bus >>> does not support clause 45 accesses). >>> The driver starts using the genphy_c45_* methods. >>> >>> At this point the driver is ready to be used on a MDIO bus capable >>> of only clause 45 accesses, but will still work on clause 22 only >>> MDIO bus. >>> >>> - I then add support for SerDes mode switching between 2500base-x >>> and sgmii, based on autonegotiated copper speed. >>> >>> All this is done so that we can support another 2.5G copper SFP >>> module, which is enabled by the last patch. >>> >> >> Has been verified that the RTL8125-integrated PHY's still work >> properly with this patch set? >> > > Hi Heiner, > > no, I wanted to send you an email to test this. I do not have the > controllers with integrates PHYs. > Quite some newer consumer mainboards come with on-board RTL8125, also a lot of cheap add-on cards with this chip is available. RTL8125 comes in different flavors, with different integrated PHY's. I have one add-on card with RTL8125 that I can use for testing. > Can you test this? > > Also do you have a controller where the rtlgen driver is used but it > only supports 1gbps ? I.e. where the PHY ID is RTL_GENERIC_PHYID > (0x001cc800). > Most of the consumer mainboards and PC's come with such a MAC/PHY controller, nowadays it's usually RTL8111h. And yes, I have such a test system. Note that there are also PHY's with this generic ID that are 100M only (on certain RTL8101 chips). > I am asking because I am told that it also is clause 45, so the drivers > can potentially be merged completely (the rtl822x_ functions can be > merged with rtlgen_ functions and everything rewritten to clause 45, > and gentphy_c45_ functions can be used). > I doubt it's C45, most likely the integrated 1G PHY's are an evolution of RTL8211f and similar PHY's. There may also be differences between all the PHY's sharing the generic id 0x001cc800. But I can't say for sure because I don't have access to any Realtek datasheets. To be 100% sure testing would have to be done on all relevant RTL8101/ RTL8168/RTL8125 chip versions. > Marek Heiner
On 20.12.2023 17:25, Marek Behún wrote: > On Wed, 20 Dec 2023 17:20:07 +0100 > Heiner Kallweit <hkallweit1@gmail.com> wrote: > >> On 20.12.2023 16:55, Marek Behún wrote: >>> Hi, >>> >>> this series reworks the realtek PHY driver's support for rtl822x >>> 2.5G transceivers: >>> >>> - First I change the driver so that the high level driver methods >>> only use clause 45 register accesses (the only clause 22 accesses >>> are left when accessing c45 registers indirectly, if the MDIO bus >>> does not support clause 45 accesses). >>> The driver starts using the genphy_c45_* methods. >>> >>> At this point the driver is ready to be used on a MDIO bus capable >>> of only clause 45 accesses, but will still work on clause 22 only >>> MDIO bus. >>> >>> - I then add support for SerDes mode switching between 2500base-x >>> and sgmii, based on autonegotiated copper speed. >>> >>> All this is done so that we can support another 2.5G copper SFP >>> module, which is enabled by the last patch. >>> >> >> Has been verified that the RTL8125-integrated PHY's still work >> properly with this patch set? >> > > Hi Heiner, > > no, I wanted to send you an email to test this. I do not have the > controllers with integrates PHYs. > > Can you test this? > > Also do you have a controller where the rtlgen driver is used but it > only supports 1gbps ? I.e. where the PHY ID is RTL_GENERIC_PHYID > (0x001cc800). > > I am asking because I am told that it also is clause 45, so the drivers > can potentially be merged completely (the rtl822x_ functions can be > merged with rtlgen_ functions and everything rewritten to clause 45, > and gentphy_c45_ functions can be used). > At least on RTL8168h indirect MMD reads return 0 always. IIRC this was the reason why the rtlgen functions use the vendor-specific registers. > Marek
On Sat, 23 Dec 2023 20:09:33 +0100 Heiner Kallweit <hkallweit1@gmail.com> wrote: > On 20.12.2023 17:25, Marek Behún wrote: > > On Wed, 20 Dec 2023 17:20:07 +0100 > > Heiner Kallweit <hkallweit1@gmail.com> wrote: > > > >> On 20.12.2023 16:55, Marek Behún wrote: > >>> Hi, > >>> > >>> this series reworks the realtek PHY driver's support for rtl822x > >>> 2.5G transceivers: > >>> > >>> - First I change the driver so that the high level driver methods > >>> only use clause 45 register accesses (the only clause 22 accesses > >>> are left when accessing c45 registers indirectly, if the MDIO bus > >>> does not support clause 45 accesses). > >>> The driver starts using the genphy_c45_* methods. > >>> > >>> At this point the driver is ready to be used on a MDIO bus capable > >>> of only clause 45 accesses, but will still work on clause 22 only > >>> MDIO bus. > >>> > >>> - I then add support for SerDes mode switching between 2500base-x > >>> and sgmii, based on autonegotiated copper speed. > >>> > >>> All this is done so that we can support another 2.5G copper SFP > >>> module, which is enabled by the last patch. > >>> > >> > >> Has been verified that the RTL8125-integrated PHY's still work > >> properly with this patch set? > >> > > > > Hi Heiner, > > > > no, I wanted to send you an email to test this. I do not have the > > controllers with integrates PHYs. > > > > Can you test this? > > > > Also do you have a controller where the rtlgen driver is used but it > > only supports 1gbps ? I.e. where the PHY ID is RTL_GENERIC_PHYID > > (0x001cc800). > > > > I am asking because I am told that it also is clause 45, so the drivers > > can potentially be merged completely (the rtl822x_ functions can be > > merged with rtlgen_ functions and everything rewritten to clause 45, > > and gentphy_c45_ functions can be used). > > > At least on RTL8168h indirect MMD reads return 0 always. > IIRC this was the reason why the rtlgen functions use the vendor-specific > registers. Looking at the code in r8169_phy_config.c, I see function rtl8168h_config_eee_phy() with three paged writes to vendor registers, but the writes do not access the same registers as the .read_mmd() methods for the PCS_EEE / AN_EEE registers in realtek.c PHY driver. It seems for now it would be best to keep the methods for paged accesses. Could you test the patchset without the patch that removes the paged access methods? The rewrite of the read_mmd / write_mmd methods should not cause problems. I am told by the realtek contact you gave me that: If FE PHY supports EEE, then it will support MMD register and it will also support use internal registers to access theses MMD registers. Marek
On 25.12.2023 11:28, Marek Behún wrote: > On Sat, 23 Dec 2023 20:09:33 +0100 > Heiner Kallweit <hkallweit1@gmail.com> wrote: > >> On 20.12.2023 17:25, Marek Behún wrote: >>> On Wed, 20 Dec 2023 17:20:07 +0100 >>> Heiner Kallweit <hkallweit1@gmail.com> wrote: >>> >>>> On 20.12.2023 16:55, Marek Behún wrote: >>>>> Hi, >>>>> >>>>> this series reworks the realtek PHY driver's support for rtl822x >>>>> 2.5G transceivers: >>>>> >>>>> - First I change the driver so that the high level driver methods >>>>> only use clause 45 register accesses (the only clause 22 accesses >>>>> are left when accessing c45 registers indirectly, if the MDIO bus >>>>> does not support clause 45 accesses). >>>>> The driver starts using the genphy_c45_* methods. >>>>> >>>>> At this point the driver is ready to be used on a MDIO bus capable >>>>> of only clause 45 accesses, but will still work on clause 22 only >>>>> MDIO bus. >>>>> >>>>> - I then add support for SerDes mode switching between 2500base-x >>>>> and sgmii, based on autonegotiated copper speed. >>>>> >>>>> All this is done so that we can support another 2.5G copper SFP >>>>> module, which is enabled by the last patch. >>>>> >>>> >>>> Has been verified that the RTL8125-integrated PHY's still work >>>> properly with this patch set? >>>> >>> >>> Hi Heiner, >>> >>> no, I wanted to send you an email to test this. I do not have the >>> controllers with integrates PHYs. >>> >>> Can you test this? >>> >>> Also do you have a controller where the rtlgen driver is used but it >>> only supports 1gbps ? I.e. where the PHY ID is RTL_GENERIC_PHYID >>> (0x001cc800). >>> >>> I am asking because I am told that it also is clause 45, so the drivers >>> can potentially be merged completely (the rtl822x_ functions can be >>> merged with rtlgen_ functions and everything rewritten to clause 45, >>> and gentphy_c45_ functions can be used). >>> >> At least on RTL8168h indirect MMD reads return 0 always. >> IIRC this was the reason why the rtlgen functions use the vendor-specific >> registers. > > Looking at the code in r8169_phy_config.c, I see function > rtl8168h_config_eee_phy() > with three paged writes to vendor registers, but the writes do not access > the same registers as the .read_mmd() methods for the PCS_EEE / AN_EEE registers > in realtek.c PHY driver. > That's some other undocumented EEE-related magic copied from the vendor driver. > It seems for now it would be best to keep the methods for paged > accesses. > > Could you test the patchset without the patch that removes the paged > access methods? > > The rewrite of the read_mmd / write_mmd methods should not cause > problems. I am told by the realtek contact you gave me that: > I tested on RTL8125A and RTL8125B, and on both indirect MMD reads return 0. I tested with reading MDIO_MMD_PCS / MDIO_PCS_EEE_ABLE. Reading this register should return 6. So it seems indirect MMD access was somehow and for whatever reason disabled by Realtek for the RTL8125-internal PHY's (provided that indirect C22 MMD access is supported by the standalone versions). Note: Internal PHY of RTL8125A has PHY ID 0x001cc800 (RTL8226 2.5Gbps PHY) Internal PHY of RTL8125B has PHY ID 0x001cc840 (RTL8226B_RTL8221B 2.5Gbps PHY) Consequence is that we can't replace reading the vendor-specific registers with standard MMD reads. > If FE PHY supports EEE, then it will support MMD register and it will > also support use internal registers to access theses MMD registers. > > Marek Heiner
Hi, this series reworks the realtek PHY driver's support for rtl822x 2.5G transceivers: - First I change the driver so that the high level driver methods only use clause 45 register accesses (the only clause 22 accesses are left when accessing c45 registers indirectly, if the MDIO bus does not support clause 45 accesses). The driver starts using the genphy_c45_* methods. At this point the driver is ready to be used on a MDIO bus capable of only clause 45 accesses, but will still work on clause 22 only MDIO bus. - I then add support for SerDes mode switching between 2500base-x and sgmii, based on autonegotiated copper speed. All this is done so that we can support another 2.5G copper SFP module, which is enabled by the last patch. Marek Alexander Couzens (1): net: phy: realtek: configure SerDes mode for rtl822x PHYs Marek Behún (14): net: phy: fail early with error code if indirect MMD access fails net: phy: export indirect MMD register accessors net: phy: realtek: rework MMD register access methods net: phy: realtek: fill .read_mmd and .write_mmd methods for all rtl822x PHYs net: mdio: add 2.5g and 5g related PMA speed constants net: phy: realtek: use generic MDIO constants net: phy: realtek: set is_c45 and fill in c45 IDs in PHY probe for rtl822x PHYs net: phy: realtek: use generic clause 45 feature reading for rtl822x PHYs net: phy: realtek: read standard MMD register for rtlgen speed capability net: phy: realtek: use generic c45 AN config with 1000baseT vendor extension for rtl822x net: phy: realtek: use generic c45 status reading with 1000baseT vendor extension for rtl822x net: phy: realtek: use generic c45 suspend/resume for rtl822x net: phy: realtek: drop .read_page and .write_page for rtl822x series net: sfp: add quirk for another multigig RollBall transceiver drivers/net/phy/phy-core.c | 54 ++++-- drivers/net/phy/realtek.c | 343 ++++++++++++++++++++++--------------- drivers/net/phy/sfp.c | 1 + include/linux/phy.h | 10 ++ include/uapi/linux/mdio.h | 2 + 5 files changed, 257 insertions(+), 153 deletions(-)