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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EE33.mail.protection.outlook.com (10.167.242.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7633.15 via Frontend Transport; Fri, 31 May 2024 21:38:48 +0000 Received: from weiserver.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 31 May 2024 16:38:46 -0500 From: Wei Huang To: , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH V2 0/9] PCIe TPH and cache direct injection support Date: Fri, 31 May 2024 16:38:32 -0500 Message-ID: <20240531213841.3246055-1-wei.huang2@amd.com> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE33:EE_|SJ0PR12MB5663:EE_ X-MS-Office365-Filtering-Correlation-Id: 67da1e8d-02fc-4422-a2f7-08dc81ba0e28 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|36860700004|376005|7416005|1800799015; X-Microsoft-Antispam-Message-Info: BVMBrWnktqBxZwc3H1lx5XO0+w8RkxPk/RDqmcxlBcmF03085zLAs17KexJIUzQHQpbKmna3v6YL9DJFrF6+yznsT6Ou+1jdVFa1nDovRJdmOi/8rVzPGoiOPOs1DlFzQyldlNCdtGysHdYfGYy18GvhEtM5A5YAZAGBHQw8GsLP71xAJO2C3Lu7Gt7iqfpu/EfISsSZErFfQ1kCZE5xe47tf4+yogeZcJTdYeE4ylTMYcjXX8imLobPeJalV/xTl0Mvz6mxSwWMN1dCBD+63vvGwT45ibkbi9Hg6f5ok11gr6Fpsv7G0R2IY63xx5qqiSJedKsIQk3ecqAXKweBgPF/VGjoP2b1R8aDuA8jUKytrk6NxJv1VBj2A57CA47AceIFSsln4D5tkvO/PAdsE0L7QicEj9x0ZAWo+Vn7zpM4KCKn/qzFaQ7Li79F+LePVRAmQq0GTAkg8eyCgZ6ZXaeuP+z066zippQ6RPh4AufoIJFT/49nXlaZsd0uwqgmf6sJqmsimrz5X9Jyzk2dCB+xwtqurejdQSl3ldQFSxE/bowuwLJMURSfTwwsEOzmvHygTuCRcWMpqXnOxYchxvAC7kJ10akXjiaZXc9wb8HvSYB050d8jTtx4o4u8EPV8IGWuSOSBDgGKAnOFc4pZnrsjIp6ApjXgbkvx6hT1L7rdhMKJkiVNJfpA0Sy4v/mjkMJQbhwGfApx5cr48EplAZyczf5vCyELputWdjId1NiI2rJDbiaB7Fzr4oTDNLAfY66zgKdoaSpHa1YLeyvsNa4+nUDrxdg7A0rqquXlqUprbiZ62ngZOFIGuK218Ib9NJfSPk8GSecXW/D3ck6aCf7hE+nvydw3ThXk/5ONCm1VFR4LVRm/GgOUAf6EUupb4oe1F54Tk7+uwarjZxPOiY6e1HZWtIxpx5IXs8k622VGQjBIaLD0wZt6K9urd+hyhDMYHqQhcH1iYMqr6D2H41zEdJCWELxsazz7rBU4zn/E9qIagisUzo8bcVwRrIsJX274LDF7U3VUhrWV0A7CS3X6CX2N2Vtv2Z9gZrcGYs7yNYVKbUplh24qZsvaArbSFIrzILAZI6CnH0XK200grcGVlD4isde4yoHcF5Yel5Cp4ml4UiVTwpgLiEzqargPoEMkUYgo/cRqQ91nGi2x/0atzn0u2BAZu59uDdWzGwRiii8L61vmAOzINNTzVQzP4QKI0XOyGuITXYIp898IiDYMRjQNacrtd9Ar7B7vTKQ9EuzATec9ySLPv0Tku8ZObhKbpiB50Ulf/JPaecPilDkaraUKdUFTiNTB+Un5ZvzxMtnvKl2jc6nacm4OTjr X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(82310400017)(36860700004)(376005)(7416005)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 May 2024 21:38:48.0118 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 67da1e8d-02fc-4422-a2f7-08dc81ba0e28 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE33.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5663 Hi All, TPH (TLP Processing Hints) is a PCIe feature that allows endpoint devices to provide optimization hints for requests that target memory space. These hints, in a format called steering tag (ST), are provided in the requester's TLP headers and allow the system hardware, including the Root Complex, to optimize the utilization of platform resources for the requests. Upcoming AMD hardware implement a new Cache Injection feature that leverages TPH. Cache Injection allows PCIe endpoints to inject I/O Coherent DMA writes directly into an L2 within the CCX (core complex) closest to the CPU core that will consume it. This technology is aimed at applications requiring high performance and low latency, such as networking and storage applications. This series introduces generic TPH support in Linux, allowing STs to be retrieved from ACPI _DSM (as defined by ACPI) and used by PCIe endpoint drivers as needed. As a demonstration, it includes an example usage in the Broadcom BNXT driver. When running on Broadcom NICs with the appropriate firmware, Cache Injection shows substantial memory bandwidth savings in real-world benchmarks. This solution is vendor-neutral, as both TPH and ACPI _DSM are industry standards. V1->V2: * Rebase on top of pci.git/for-linus (6.10-rc1) * Address mismatched data types reported by Sparse (Sparse checking passed) * Add a new API, pcie_tph_intr_vec_supported(), for checking IRQ mode support * Skip bnxt affinity notifier registration if pcie_tph_intr_vec_supported()=false * Minor fixes in bnxt driver (i.e. warning messages) Manoj Panicker (1): bnxt_en: Add TPH support in BNXT driver Michael Chan (1): bnxt_en: Pass NQ ID to the FW when allocating RX/RX AGG rings Wei Huang (8): PCI: Introduce PCIe TPH support framework PCI: Add TPH related register definition PCI/TPH: Implement a command line option to disable TPH PCI/TPH: Implement a command line option to force No ST Mode PCI/TPH: Introduce API functions to manage steering tags PCI/TPH: Retrieve steering tag from ACPI _DSM PCI/TPH: Add TPH documentation Documentation/PCI/index.rst | 1 + Documentation/PCI/tph.rst | 57 ++ .../admin-guide/kernel-parameters.txt | 2 + Documentation/driver-api/pci/pci.rst | 3 + drivers/net/ethernet/broadcom/bnxt/bnxt.c | 62 +- drivers/net/ethernet/broadcom/bnxt/bnxt.h | 4 + drivers/pci/pci-driver.c | 12 +- drivers/pci/pci.c | 24 + drivers/pci/pci.h | 6 + drivers/pci/pcie/Kconfig | 10 + drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/tph.c | 582 ++++++++++++++++++ drivers/pci/probe.c | 1 + drivers/vfio/pci/vfio_pci_config.c | 7 +- include/linux/pci-tph.h | 78 +++ include/linux/pci.h | 6 + include/uapi/linux/pci_regs.h | 35 +- 17 files changed, 881 insertions(+), 10 deletions(-) create mode 100644 Documentation/PCI/tph.rst create mode 100644 drivers/pci/pcie/tph.c create mode 100644 include/linux/pci-tph.h