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Tue, 1 Oct 2024 03:37:33 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Simon Horman , Tariq Toukan Subject: [PATCH net-next V2 0/6] net/mlx5: hw counters refactor Date: Tue, 1 Oct 2024 13:37:03 +0300 Message-ID: <20241001103709.58127-1-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CF:EE_|MW4PR12MB7192:EE_ X-MS-Office365-Filtering-Correlation-Id: e8814528-11bd-498c-925d-08dce2051748 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: yq/rgZZ4kXBjq2ZvKQxiAl+xKUxb1opJtb236E2//MadU15KISAo/nfTedYQetA+MWx02s9TJWEx0T3INkI6xnTOi9yZJiXxGZh79Ap6tkRAp+LpLlJ2XqXg8pMOB1U5RVpj7sfOTs0s+YG4r4Eh04rmxM7u9mGxbhOgvRsahvySfOHnAcYXaqBW/1C5gQppE1d8LeqI0AtRynQgxTBW3KI8AtiiY0AB9BSzeZPp5POWrky0q7gMBcokq9jKc/Zw0NLatyLPC03xy8pBXK6q3YArKCMB7/1KVlhO0AFzQkt739rRegVj3YqsQ80EyrtWkl8X2FVOLN7ftKA60YL34UWGb1KYBdw/+GaDTRpk/zCnQtrpHqJvOhwn/kRtBuvZIkaAC5tQExv09HadnuoRfV4c4wYlf/k+h07cJ4i/PsFr9/JzC3hTEQ0cKA7VJJnl+olfgsIx2MoNGuo4Z15hcELNnUoEgOguGZ1Ue+pdD5apRmfuy48DPm13DPsdhoQKJIT1+goBQ/DafvHcUhOcl9qe5O3Re6DKjTbDLT4YNfjI1Ac63hhrMC7pf6Y0nv/x/6RKmyZfcarNOjjvvddrcn9UOkNTic3NyuVh4ihrACobMoe6KUD4RLSKm1bo4labHkG55UmVrVKfhw+TpXbshi0QZN2jJ6CdsZ6CRHCu09Vc8aR+ecHf7KKlDTT6kCQ76Ha32tf+n3yh56vNRrglPRLaudLG5eutBz75pVhfMeNVecViLaffj/oQU2kAyWj0TzHNlRtqL5A5IiIZ3sZFQaNAXDkdmS/pSxy8ekXKiGslu74jwtsfrFWYthqefPcp3JKfve7+nXpebbBWbmeSe+uck98bjLxg9x0v4EybHEisFrZ9K/53GGlcu+wVU4UodnZnYEP9Z74P13VCK7jr0+LDOMWrZwVDX2gO7AHZxwy7/pJejDhhJnoxuuXNRfJpP2Bafxv3GAzsWd4h7weTgPLlvj+i3OE6RhmzaHxU06qTZ1h+IXKylBD/l7FYh4VukqQl1747y6g87wNK+gNqXYXawlvTWRaiadYxNg4BIWRcn/1tnXCavGmPTRk/HF17bsGtj59tR4BbRkX0i2Ub81uzX2uJbVweJOK3hOfgvwSdSLs0hXj58tTF5jTZGP+8D+dMM8TB1poEIdKCpjd+P0jqdQrfX/GDS9bpWJTZGJg/S/BLH7WREKYuRkxGxndl6OxtroUmoIa0fc4O3HBNtKQ/Sx5SHx6u5HvZdIw0A7Ppkn9J3WZVsXiCtvL6LT9hykoW5GSzWOFOVK4ZS1gZKbGlzWfTkpSTXHemr14+pk08m2e33NoqzhcH/MqGj2diMjDYXpOzy8/FN+y0SsCCQJKG0fIPHbl1QhaTOp4VGBlePsR4peg3Sa9iDku+7HVqjPncvRm++k6zONjxs+PPBbv9w1FVB8w2G8cdX2gITRmgy0XEghaKBYPr+dABvsJF X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2024 10:37:47.2801 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e8814528-11bd-498c-925d-08dce2051748 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7192 X-Patchwork-Delegate: kuba@kernel.org This is a patchset re-post, see: https://lore.kernel.org/netdev/20240815054656.2210494-7-tariqt@nvidia.com/T/ In this patchset, Cosmin refactors hw counters and solves perf scaling issue. Series generated against: commit c824deb1a897 ("cxgb4: clip_tbl: Fix spelling mistake "wont" -> "won't"") HW counters are central to mlx5 driver operations. They are hardware objects created and used alongside most steering operations, and queried from a variety of places. Most counters are queried in bulk from a periodic task in fs_counters.c. Counter performance is important and as such, a variety of improvements have been done over the years. Currently, counters are allocated from pools, which are bulk allocated to amortize the cost of firmware commands. Counters are managed through an IDR, a doubly linked list and two atomic single linked lists. Adding/removing counters is a complex dance between user contexts requesting it and the mlx5_fc_stats_work task which does most of the work. Under high load (e.g. from connection tracking flow insertion/deletion), the counter code becomes a bottleneck, as seen on flame graphs. Whenever a counter is deleted, it gets added to a list and the wq task is scheduled to run immediately to actually delete it. This is done via mod_delayed_work which uses an internal spinlock. In some tests, waiting for this spinlock took up to 66% of all samples. This series refactors the counter code to use a more straight-forward approach, avoiding the mod_delayed_work problem and making the code easier to understand. For that: - patch #1 moves counters data structs to a more appropriate place. - patch #2 simplifies the bulk query allocation scheme by using vmalloc. - patch #3 replaces the IDR+3 lists with an xarray. This is the main patch of the series, solving the spinlock congestion issue. - patch #4 removes an unnecessary cacheline alignment causing a lot of memory to be wasted. - patches #5 and #6 are small cleanups enabled by the refactoring. Regards, Tariq V2: - no changes, re-posting. Cosmin Ratiu (6): net/mlx5: hw counters: Make fc_stats & fc_pool private net/mlx5: hw counters: Use kvmalloc for bulk query buffer net/mlx5: hw counters: Replace IDR+lists with xarray net/mlx5: hw counters: Drop unneeded cacheline alignment net/mlx5: hw counters: Don't maintain a counter count net/mlx5: hw counters: Remove mlx5_fc_create_ex .../ethernet/mellanox/mlx5/core/en/tc_ct.c | 2 +- .../ethernet/mellanox/mlx5/core/fs_counters.c | 387 +++++++----------- include/linux/mlx5/driver.h | 33 +- include/linux/mlx5/fs.h | 3 - 4 files changed, 147 insertions(+), 278 deletions(-)