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[net-next,0/2] dpll: expose clock quality level

Message ID 20241009122547.296829-1-jiri@resnulli.us (mailing list archive)
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Series dpll: expose clock quality level | expand

Message

Jiri Pirko Oct. 9, 2024, 12:25 p.m. UTC 
From: Jiri Pirko <jiri@nvidia.com>

Some device driver might know the quality of the clock it is running.
In order to expose the information to the user, introduce new netlink
attribute and dpll device op. Implement the op in mlx5 driver.

Example:
$ ./tools/net/ynl/cli.py --spec Documentation/netlink/specs/dpll.yaml --dump device-get
[{'clock-id': 540663412652420550,
  'clock-quality-level': 'eeec',      <<<<<<<<<<<<<<<<<<<<<<<<<<
  'id': 0,
  'lock-status': 'unlocked',
  'lock-status-error': 'none',
  'mode': 'manual',
  'mode-supported': ['manual'],
  'module-name': 'mlx5_dpll',
  'type': 'eec'}]

Jiri Pirko (2):
  dpll: add clock quality level attribute and op
  net/mlx5: DPLL, Add clock quality level op implementation

 Documentation/netlink/specs/dpll.yaml         | 28 +++++++
 drivers/dpll/dpll_netlink.c                   | 22 +++++
 .../net/ethernet/mellanox/mlx5/core/dpll.c    | 82 +++++++++++++++++++
 include/linux/dpll.h                          |  4 +
 include/uapi/linux/dpll.h                     | 21 +++++
 5 files changed, 157 insertions(+)