From patchwork Fri Oct 18 20:30:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sai Krishna X-Patchwork-Id: 13842335 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C09C205AD0; Fri, 18 Oct 2024 20:31:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729283477; cv=none; b=KaJjbLH91eRR4C31ptwvfVeJOoPjQL70s8yQ6Ct2wjuP0qqWodHD63vUVyK2ELIGqABLT/tfw06O/fNBhXcjKgZGeNXp5XBvjkD/KTu8k94UGzcmQOMbP9XfZe/U41th52AmIvSZaEszNEZPxEhgx8O9gabQ3fUp9EoEQeq2fXI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729283477; c=relaxed/simple; bh=jxYSW0+WyHMobClrGQdCqB0UMbeyFIjEC0GrZW/fC9Y=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=T2RHrw4Fy+U+RsYTfy6S5LrB0Hr0OYh3JypXRslXKTytPrXgLnHCSIGCzB1ZXA1PacqDHveu7a9Jw8o3BAQPyc7vdRQJ0Zhd1y+MxvmuJo0aJKsEgA2HeijEWzDZ9f+f07VWZZnGBM8orOAGanca5oGQjo4KxhMq4xSdqHzCYAU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=NE7xqnXO; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="NE7xqnXO" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49IA8c1L032610; Fri, 18 Oct 2024 13:31:06 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=pfpt0220; bh=A0Q/vfb2zuwjqqaxDrXkBkV HcAMRGfStVQ8Ldd9N6bE=; b=NE7xqnXOtjY0k5PHMefhNvx4Rd4AJwMWVI7EmVD Y/CsI7mCJKZKT/ypxkVzzd7/K747NJ0MKM1qGhQ++JN06YaebuliZVFgbAQ1tj53 Aig/QozkCUB9tuvNzVn51/eN90ZD/3WxuzeWg3NuCsLU2baK4A+YyNew97HmvuFi bJx/ir8Jd29WebGvZpNofYZvJxgYyqgzioi0PLnjiXMZyC4l1UTPCzuASJ6+/OzX UjN5gW5hqXf5/VcriYm1GGVo+SgVUHTrJJnkZvnaHPikz9QaFEn8pDk2de014Z7b vP7VNfEbRhG8od5BwFhB4KX75rGrfDWBjVCBVMouNV3wGvQ== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 42bnnbhbp0-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Oct 2024 13:31:06 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 18 Oct 2024 13:31:05 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 18 Oct 2024 13:31:05 -0700 Received: from hyd1425.marvell.com (unknown [10.29.37.152]) by maili.marvell.com (Postfix) with ESMTP id 11E313F704C; Fri, 18 Oct 2024 13:31:00 -0700 (PDT) From: Sai Krishna To: , , , , , , , , , , , CC: Sai Krishna Subject: [net-next PATCH 0/6] CN20K silicon with mbox support Date: Sat, 19 Oct 2024 02:00:52 +0530 Message-ID: <20241018203058.3641959-1-saikrishnag@marvell.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: eaZWN6p9uiWHU477aeG15V6wP_JKPE4W X-Proofpoint-ORIG-GUID: eaZWN6p9uiWHU477aeG15V6wP_JKPE4W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Patchwork-Delegate: kuba@kernel.org CN20K is the next generation silicon in the Octeon series with various improvements and new features. Along with other changes the mailbox communication mechanism between RVU (Resource virtualization Unit) SRIOV PFs/VFs with Admin function (AF) has also gone through some changes. Some of those changes are - Separate IRQs for mbox request and response/ack. - Configurable mbox size, default being 64KB. - Ability for VFs to communicate with RVU AF instead of going through parent SRIOV PF. Due to more memory requirement due to configurable mbox size, mbox memory will now have to be allocated by - AF (PF0) for communicating with other PFs and all VFs in the system. - PF for communicating with it's child VFs. On previous silicons mbox memory was reserved and configured by firmware. This patch series add basic mbox support for AF (PF0) <=> PFs and PF <=> VFs. AF <=> VFs communication and variable mbox size support will come in later. Patch #1 Supported co-existance of bit encoding PFs and VFs in 16-bit hardware pcifunc format between CN20K silicon and older octeon series. Also exported PF,VF masks and shifts present in mailbox module to all other modules. Patch #2 Added basic mbox operation APIs and structures to support both CN20K and previous version of silicons. Patch #3 This patch adds support for basic mbox infrastructure implementation for CN20K silicon in AF perspective. There are few updates w.r.t MBOX ACK interrupt and offsets in CN20k. Patch #4 Added mbox implementation between NIC PF and AF for CN20K. Patch #5 Added mbox communication support between AF and AF's VFs. Patch #6 This patch adds support for MBOX communication between NIC PF and its VFs. Sai Krishna (5): octeontx2-af: CN20k basic mbox operations and structures octeontx2-af: CN20k mbox to support AF REQ/ACK functionality octeontx2-pf: CN20K mbox REQ/ACK implementation for NIC PF octeontx2-af: CN20K mbox implementation for AF's VF octeontx2-pf: CN20K mbox implementation between PF-VF Subbaraya Sundeep (1): octeontx2: Set appropriate PF, VF masks and shifts based on silicon .../ethernet/marvell/octeontx2/af/Makefile | 3 +- .../ethernet/marvell/octeontx2/af/cn20k/api.h | 34 ++ .../marvell/octeontx2/af/cn20k/mbox_init.c | 423 ++++++++++++++++++ .../ethernet/marvell/octeontx2/af/cn20k/reg.h | 81 ++++ .../marvell/octeontx2/af/cn20k/struct.h | 40 ++ .../net/ethernet/marvell/octeontx2/af/mbox.c | 123 ++++- .../net/ethernet/marvell/octeontx2/af/mbox.h | 13 + .../net/ethernet/marvell/octeontx2/af/rvu.c | 187 +++++--- .../net/ethernet/marvell/octeontx2/af/rvu.h | 55 ++- .../marvell/octeontx2/af/rvu_struct.h | 6 +- .../ethernet/marvell/octeontx2/nic/Makefile | 2 +- .../ethernet/marvell/octeontx2/nic/cn10k.c | 18 +- .../ethernet/marvell/octeontx2/nic/cn10k.h | 1 + .../ethernet/marvell/octeontx2/nic/cn20k.c | 254 +++++++++++ .../ethernet/marvell/octeontx2/nic/cn20k.h | 17 + .../marvell/octeontx2/nic/otx2_common.h | 35 +- .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 145 ++++-- .../ethernet/marvell/octeontx2/nic/otx2_reg.h | 49 +- .../ethernet/marvell/octeontx2/nic/otx2_vf.c | 44 +- 19 files changed, 1383 insertions(+), 147 deletions(-) create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/cn20k/api.h create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/cn20k/reg.h create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/cn20k/struct.h create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/cn20k.h