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[93.34.91.161]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-432aa6b60e9sm20444155e9.14.2024.11.06.04.23.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 04:23:19 -0800 (PST) From: Christian Marangi To: Christian Marangi , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Matthias Brugger , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@airoha.com Subject: [net-next PATCH v3 0/3] net: dsa: Add Airoha AN8855 support Date: Wed, 6 Nov 2024 13:22:35 +0100 Message-ID: <20241106122254.13228-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org This small series add the initial support for the Airoha AN8855 Switch. It's a 5 port Gigabit Switch with SGMII/HSGMII upstream port. This is starting to get in the wild and there are already some router having this switch chip. It's conceptually similar to mediatek switch but register and bits are different. And there is that massive Hell that is the PCS configuration. Saddly for that part we have absolutely NO documentation currently. There is this special thing where PHY needs to be calibrated with values from the switch efuse. (the thing have a whole cpu timer and MCU) Some cleanup API are used and one extra patch for mdio_mutex_nested is introduced. As suggested some time ago, the use of such API is limited to scoped variants and not the guard ones. Posting as RFC as I expect in later version to add additional feature but this is already working and upstream-ready. So this is really to have a review of the very basic features and if I missed anything in recent implementation of DSA. Changes v3: - Out of RFC - Switch PHY code to select_page API - Better describe masks and bits in PHY driver for ADC register - Drop raw values and use define for mii read/write - Switch to absolute PHY address - Replace raw values with mask and bits for pcs_config - Fix typo for ext-surge property name - Drop support for relocating Switch base PHY address on the bus Changes v2: - Drop mutex guard patch - Drop guard usage in DSA driver - Use __mdiobus_write/read - Check return condition and return errors for mii read/write - Fix wrong logic for EEE - Fix link_down (don't force link down with autoneg) - Fix forcing speed on sgmii autoneg - Better document link speed for sgmii reg - Use standard define for sgmii reg - Imlement nvmem support to expose switch EFUSE - Rework PHY calibration with the use of NVMEM producer/consumer - Update DT with new NVMEM property - Move aneg validation for 2500-basex in pcs_config - Move r50Ohm table and function to PHY driver Christian Marangi (3): dt-bindings: net: dsa: Add Airoha AN8855 Gigabit Switch documentation net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY .../bindings/net/dsa/airoha,an8855.yaml | 242 ++ MAINTAINERS | 11 + drivers/net/dsa/Kconfig | 9 + drivers/net/dsa/Makefile | 1 + drivers/net/dsa/an8855.c | 2054 +++++++++++++++++ drivers/net/dsa/an8855.h | 628 +++++ drivers/net/phy/Kconfig | 5 + drivers/net/phy/Makefile | 1 + drivers/net/phy/air_an8855.c | 278 +++ 9 files changed, 3229 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855.yaml create mode 100644 drivers/net/dsa/an8855.c create mode 100644 drivers/net/dsa/an8855.h create mode 100644 drivers/net/phy/air_an8855.c