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Mon, 09 Dec 2024 00:21:48 -0800 (PST) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7b6d7886351sm57211985a.86.2024.12.09.00.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2024 00:21:48 -0800 (PST) From: Inochi Amaoto To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Richard Cochran Cc: Inochi Amaoto , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH 0/2] clk: sophgo: add SG2044 clock controller support Date: Mon, 9 Dec 2024 16:21:29 +0800 Message-ID: <20241209082132.752775-1-inochiama@gmail.com> X-Mailer: git-send-email 2.47.1 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The clock controller of SG2044 provides multiple clocks for various IPs on the SoC, including PLL, mux, div and gates. As the PLL and div have obvious changed and do not fit the framework of SG2042, a new implement is provided to handle these. Inochi Amaoto (2): dt-bindings: clock: sophgo: add clock controller for SG2044 clk: sophgo: Add clock controller support for SG2044 SoC .../bindings/clock/sophgo,sg2044-clk.yaml | 40 + drivers/clk/sophgo/Kconfig | 11 + drivers/clk/sophgo/Makefile | 1 + drivers/clk/sophgo/clk-sg2044.c | 2275 +++++++++++++++++ drivers/clk/sophgo/clk-sg2044.h | 62 + include/dt-bindings/clock/sophgo,sg2044-clk.h | 170 ++ 6 files changed, 2559 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml create mode 100644 drivers/clk/sophgo/clk-sg2044.c create mode 100644 drivers/clk/sophgo/clk-sg2044.h create mode 100644 include/dt-bindings/clock/sophgo,sg2044-clk.h --- 2.47.1