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Mon, 3 Feb 2025 13:36:02 -0800 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Tariq Toukan Subject: [PATCH net-next 00/15] Support one PTP device per hardware clock Date: Mon, 3 Feb 2025 23:35:01 +0200 Message-ID: <20250203213516.227902-1-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F68:EE_|SN7PR12MB7225:EE_ X-MS-Office365-Filtering-Correlation-Id: cda8d495-3e09-422d-7012-08dd449ace2a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: tFF28etWnj5w+bLh5yFvsbykUoT+s9RDLp3GhHEVoybbgaB3RFCnB6FwJoCbycXFcVgwlDMUuldPOJEqnccywXvqK+eW53RxMRXQ1MQYEFgUMyjhU/j4MtCcx6KWzHWF6dCTxwuZoDFg+6vlc9eoDRIn6LL1plqfbyogfO3nWtMkSspXWp4k5BJ/VXU+SQDDdBlc2LxiQruG6IREqvOtTyZYOfGnuYsZNEgWiPkWgmbLHJtTXcvc+WAyMSLrE7+fDKWM8u4fgfklUUZXZ9O6GkVH6QcKjQ4FnVG7d+2YosJtxf76g3ZkUNQudD8jmSAhx31+EvwPQv3zEY3diwpVJeZwMy/OCveWR0QOY5nUeaAbV0k2qam1HBneLnm1H26zd2lnGLD+5cMWS1E4ZK1rtWYnsIAShybx+miK8LaHOFSV1xRED6cooUr1UzGAzopQ9obFzC7ctnN3YJfYTS/RRYD5lsHK65w5o8GX4tM7YAg+rkSJ6d8Xw2NrZeZJ3H77K2qKcOQTItxZZGrG6qR26FVxmCaKuD57/4CsrNlHMU9PY5wD8LQ1Ijm5xv1GSsDiFZaOaw3BAPf65sfoJX0nXH42hOfKmPaOrwQjwBhW3HiMZScZYJk9DvG9Y6ylidW/3Xcn6zYhTW831dYeqjRjyDu2yO3lZz6Rnv4ClnZZI1/bRhlLzuCgTzkggNIVXyvve2yir2L26FNUOYKjEmxlk6l45LDE7fU3APX/HLI8qFcPoM4V6V7D1rNKzDQQ/AZ6IUMvSsNpiVkA6VsJJP+ICsucW0PQIuCaiY07KkOc7FrcdIMa3jwa1xCB1Bp7SBU8QYY/FIhMgdoRO5mMWhRDjz0748V9TuveKIlrGwPHqnDZERf0uEXkC+MUklM3dkMqdrq5XljTmjehNiVaPP68xR8YQ95PyfEDpBbp90WqgMItwxo1u8Cta3pcvLrKv9qshOHENsC+QkUxZ4eGTp+DUo1RqTI3YfLXDta1mBG1uEmptze2TtkRls9v+0Z+A2f7PzOGXux6EM7FZcZcns3SpfZ4FHqxJX/hHrh5n4XEDHjr/ryHZDQYQj6ESA1odxo6ifZC43KhvCbZzuKY7y3OsPJrGTOzf+JDn1Vt+ggvBeUyRw3kfhtl5gObZcvZRiqDHqcGeW+HbzP/83Bvl6yUsbGznzO9pNuS2QfxJuLYbjrisWZySXYGxP2+CL33NqzKPTBMPRHc2rVsmxbz37EDNtv10opbaC+vqAprrAIinEyyIZl+LtnkiZ2FdUcXzZrCTmvdkFJ/DxuLugvwGVwBIdshClIdYQHw7yl4sAAnueXOnW7a7adH9vHJajIPptJhfQSIflLCtGU854v8Sm8UF1fMCto7Rw52RvAvKTU/h3Hrb2VVziXtR3tPS+mOrwlsNYiqifCEs8rSXMgQXIa/r8gw6xZBrbIEETphkTiAjzZfzcDkWqvi3iU/s/23R1hCDxB40Ez+fmO4tY1YoKbtZYM/tjcYWa/T7ZK/jbcGIO4= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:36:22.9768 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cda8d495-3e09-422d-7012-08dd449ace2a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F68.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7225 X-Patchwork-Delegate: kuba@kernel.org Hi, This series contains two features from Jianbo, followed by simple cleanups. Patches 1-9 by Jianbo add support for one PTP device per hardware clock, described below [1]. Patches 10-12 by Jianbo add support for 200Gbps per-lane link modes in kernel and mlx5 driver. Patches 13-15 are simple cleanups by Gal and Carolina. Regards, Tariq [1] PHC (PTP hardware clock) is normally shared by multiple functions (PF/VF/SF). mlx5 driver currently creates a separate PTP device for each network interface that shares one PHC. PHC can be configured to work as free running mode or real time mode. In this series, only one PTP device is created for the shared PHC when it is running in real time mode. To support this feature, * Firmware needs to support clock identity. When functions share a PHC, the clock identities they query are same. * Driver dynamically allocates mlx5_clock to represent a PHC. * New devcom component is added for hardware clock. Functions are grouped by the identity, and one mlx5_clock is allocated and shared by the functions with the same identity. * When PTP device accesses PHC by its callbacks, the first function in the clock devcom list is selected to send commands to firmware. * PPS IN event is armed on one function. It should be re-armed on the other one when current is unloaded. Carolina Jubran (1): net/mlx5e: Avoid WARN_ON when configuring MQPRIO with HTB offload enabled Gal Pressman (2): net/mlx5: Remove stray semicolon in LAG port selection table creation net/mlx5e: Remove unused mlx5e_tc_flow_action struct Jianbo Liu (12): net/mlx5: Add helper functions for PTP callbacks net/mlx5: Change parameters for PTP internal functions net/mlx5: Add init and destruction functions for a single HW clock net/mlx5: Add API to get mlx5_core_dev from mlx5_clock net/mlx5: Change clock in mlx5_core_dev to mlx5_clock pointer net/mlx5: Add devcom component for the clock shared by functions net/mlx5: Move PPS notifier and out_work to clock_state net/mlx5: Support one PTP device per hardware clock net/mlx5: Generate PPS IN event on new function for shared clock ethtool: Add support for 200Gbps per lane link modes net/mlx5: Add support for 200Gbps per lane link modes net/mlx5e: Support FEC settings for 200G per lane link modes .../net/ethernet/mellanox/mlx5/core/en/port.c | 64 +- .../net/ethernet/mellanox/mlx5/core/en/port.h | 1 + .../net/ethernet/mellanox/mlx5/core/en/ptp.c | 4 +- .../mellanox/mlx5/core/en/tc/act/act.h | 5 - .../net/ethernet/mellanox/mlx5/core/en/trap.c | 2 +- .../net/ethernet/mellanox/mlx5/core/en/xdp.c | 4 +- .../mellanox/mlx5/core/en/xsk/setup.c | 2 +- .../ethernet/mellanox/mlx5/core/en_ethtool.c | 22 + .../net/ethernet/mellanox/mlx5/core/en_main.c | 11 +- .../mellanox/mlx5/core/lag/port_sel.c | 2 +- .../ethernet/mellanox/mlx5/core/lib/clock.c | 582 ++++++++++++++---- .../ethernet/mellanox/mlx5/core/lib/clock.h | 39 +- .../ethernet/mellanox/mlx5/core/lib/devcom.h | 1 + .../net/ethernet/mellanox/mlx5/core/main.c | 15 +- .../net/ethernet/mellanox/mlx5/core/port.c | 3 + drivers/net/phy/phy-core.c | 20 +- include/linux/mlx5/driver.h | 33 +- include/linux/mlx5/port.h | 3 + include/uapi/linux/ethtool.h | 18 + net/ethtool/common.c | 42 ++ 20 files changed, 701 insertions(+), 172 deletions(-) base-commit: 2014c95afecee3e76ca4a56956a936e23283f05b