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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3997f99579bsm18390328f8f.19.2025.03.26.16.35.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Mar 2025 16:35:44 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , =?utf-8?q?Marek_Beh=C3=BAn?= , Eric Woudstra , Daniel Golle , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next RFC PATCH v3 0/4] net: phy: Add support for new Aeonsemi PHYs Date: Thu, 27 Mar 2025 00:35:00 +0100 Message-ID: <20250326233512.17153-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Add support for new Aeonsemi 10G C45 PHYs. These PHYs intergate an IPC to setup some configuration and require special handling to sync with the parity bit. The parity bit is a way the IPC use to follow correct order of command sent. Supported PHYs AS21011JB1, AS21011PB1, AS21010JB1, AS21010PB1, AS21511JB1, AS21511PB1, AS21510JB1, AS21510PB1, AS21210JB1, AS21210PB1 that all register with the PHY ID 0x7500 0x7500 before the firmware is loaded. The big special thing about this PHY is that it does provide a generic PHY ID in C45 register that change to the correct one one the firmware is loaded. In practice: - MMD 0x7 ID 0x7500 0x9410 -> FW LOAD -> ID 0x7500 0x9422 To handle this, we operate on .match_phy_device where we check the PHY ID, if the ID match the generic one, we load the firmware and we return 0 (PHY driver doesn't match). Then PHY core will try the next PHY driver in the list and this time the PHY is correctly filled in and we register for it. To help in the matching and not modify part of the PHY device struct, .match_phy_device is extended to provide also the current phy_driver is trying to match for. This add the extra benefits that some other PHY can simplify their .match_phy_device OP. Changes v3: - Correct typo intergate->intergate - Try to reduce to 80 column (where possible... define become unreasable if split) - Rework to new .match_phy_device implementation - Init active_low_led and fix other minor smatch war - Drop inline tag (kbot doesn't like it but not reported by checkpatch???) Changes v2: - Move to RFC as net-next closed :( - Add lock for IPC command - Better check size values from IPC - Add PHY ID for all supported PHYs - Drop .get_feature (correct values are exported by standard regs) - Rework LED event to enum - Update .yaml with changes requested (firmware-name required for generic PHY ID) - Better document C22 in C45 - Document PHY name logic - Introduce patch to load PHY 2 times Christian Marangi (4): net: phy: pass PHY driver to .match_phy_device OP net: phy: bcm87xx: simplify .match_phy_device OP net: phy: Add support for Aeonsemi AS21xxx PHYs dt-bindings: net: Document support for Aeonsemi PHYs .../bindings/net/aeonsemi,as21xxx.yaml | 122 ++ MAINTAINERS | 7 + drivers/net/phy/Kconfig | 12 + drivers/net/phy/Makefile | 1 + drivers/net/phy/as21xxx.c | 1048 +++++++++++++++++ drivers/net/phy/bcm87xx.c | 14 +- drivers/net/phy/icplus.c | 6 +- drivers/net/phy/marvell10g.c | 12 +- drivers/net/phy/micrel.c | 6 +- drivers/net/phy/nxp-tja11xx.c | 6 +- drivers/net/phy/phy_device.c | 2 +- drivers/net/phy/realtek/realtek_main.c | 27 +- drivers/net/phy/teranetics.c | 3 +- include/linux/phy.h | 3 +- 14 files changed, 1238 insertions(+), 31 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml create mode 100644 drivers/net/phy/as21xxx.c