Show patches with: Series = Xilinx axienet fixes       |   7 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[net,7/7] net: axienet: increase default TX ring size to 128 Xilinx axienet fixes - - - 15-1 2022-01-11 Robert Hancock netdev Superseded
[net,6/7] net: axienet: fix for TX busy handling Xilinx axienet fixes - - - 1411 2022-01-11 Robert Hancock netdev Superseded
[net,5/7] net: axienet: fix number of TX ring slots for available check Xilinx axienet fixes - - - 15-1 2022-01-11 Robert Hancock netdev Superseded
[net,4/7] net: axienet: Fix TX ring slot available check Xilinx axienet fixes - - - 15-1 2022-01-11 Robert Hancock netdev Superseded
[net,3/7] net: axienet: limit minimum TX ring size Xilinx axienet fixes - - - 15-1 2022-01-11 Robert Hancock netdev Superseded
[net,2/7] net: axienet: add missing memory barriers Xilinx axienet fixes - - - 1411 2022-01-11 Robert Hancock netdev Superseded
[net,1/7] net: axienet: Reset core before accessing MAC and wait for core ready Xilinx axienet fixes - - - 1321 2022-01-11 Robert Hancock netdev Superseded