Show patches with: Series = Xilinx axienet fixes       |   9 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[net,v2,9/9] net: axienet: increase default TX ring size to 128 Xilinx axienet fixes - - - 16-- 2022-01-12 Robert Hancock netdev Superseded
[net,v2,8/9] net: axienet: fix for TX busy handling Xilinx axienet fixes - - - 151- 2022-01-12 Robert Hancock netdev Superseded
[net,v2,7/9] net: axienet: fix number of TX ring slots for available check Xilinx axienet fixes - - - 16-- 2022-01-12 Robert Hancock netdev Superseded
[net,v2,6/9] net: axienet: Fix TX ring slot available check Xilinx axienet fixes - - - 16-- 2022-01-12 Robert Hancock netdev Superseded
[net,v2,5/9] net: axienet: limit minimum TX ring size Xilinx axienet fixes - - - 15-1 2022-01-12 Robert Hancock netdev Superseded
[net,v2,4/9] net: axienet: add missing memory barriers Xilinx axienet fixes - - - 151- 2022-01-12 Robert Hancock netdev Superseded
[net,v2,3/9] net: axienet: reset core on initialization prior to MDIO access Xilinx axienet fixes - 1 - 16-- 2022-01-12 Robert Hancock netdev Superseded
[net,v2,2/9] net: axienet: Wait for PhyRstCmplt after core reset Xilinx axienet fixes - 1 - 151- 2022-01-12 Robert Hancock netdev Superseded
[net,v2,1/9] net: axienet: increase reset timeout Xilinx axienet fixes - 1 - 16-- 2022-01-12 Robert Hancock netdev Superseded