Show patches with: Series = Xilinx axienet fixes       |   9 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[net,v3,9/9] net: axienet: increase default TX ring size to 128 Xilinx axienet fixes - - - 15-1 2022-01-18 Robert Hancock netdev Accepted
[net,v3,8/9] net: axienet: fix for TX busy handling Xilinx axienet fixes - - - 1411 2022-01-18 Robert Hancock netdev Accepted
[net,v3,7/9] net: axienet: fix number of TX ring slots for available check Xilinx axienet fixes - - - 15-1 2022-01-18 Robert Hancock netdev Accepted
[net,v3,6/9] net: axienet: Fix TX ring slot available check Xilinx axienet fixes - - - 15-1 2022-01-18 Robert Hancock netdev Accepted
[net,v3,5/9] net: axienet: limit minimum TX ring size Xilinx axienet fixes - - - 15-1 2022-01-18 Robert Hancock netdev Accepted
[net,v3,4/9] net: axienet: add missing memory barriers Xilinx axienet fixes - - - 1411 2022-01-18 Robert Hancock netdev Accepted
[net,v3,3/9] net: axienet: reset core on initialization prior to MDIO access Xilinx axienet fixes - 1 - 16-- 2022-01-18 Robert Hancock netdev Accepted
[net,v3,2/9] net: axienet: Wait for PhyRstCmplt after core reset Xilinx axienet fixes - 1 - 1411 2022-01-18 Robert Hancock netdev Accepted
[net,v3,1/9] net: axienet: increase reset timeout Xilinx axienet fixes - 1 - 15-1 2022-01-18 Robert Hancock netdev Accepted