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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 06/17] mlxsw: spectrum_fid: Add an op for flood table initialization Date: Tue, 28 Nov 2023 16:50:39 +0100 Message-ID: <06f71415eec75811585ec597e1dd101b6dff77e7.1701183892.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3D:EE_|SJ1PR12MB6146:EE_ X-MS-Office365-Filtering-Correlation-Id: 81dbc293-8ee0-4dc1-dc1d-08dbf029e3bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rUSKJEcZ3cSCWjbQctQm0Rb/3JsYN5578cRzw8VJ40nEis/5hhNi4Y0VdZKDGeCESY9i5J7KpQIfl9i+Ni8gHmPeKzbC2zTwSLZMtejYlJCta6tZ0bybKP37ZTroFMkvx1C7vz9/lI1xXCbHkC/GcT4S3B1DALrRPbtUd2+KVFk6Z7gVog3I7uVvNQIijC9yrZEvgMg4OPShi0tllhpmI3lift3Yk0l7CQGBshWLkwcuhykaQ3JLap3zPZsXzE6Oa7Wz/HxrbJrk61cGH9k/JaJ0KbSt8MdyJJjyuRlEGMWVZ+Bqld3n4gfoNIic59rZDmkjU4Il2Hnx9kikPvpR/62A6yrswg7Q9jykHpEeM//5vyQtQW/JZebHVTUs1h8cP3pEA0R3FGi7OieGuQyp6W3R5vBcES4XX+iF9slwT0Zo9vBxAfIMxJz8pTUFXSd0h9t1KvG2guCXEXSBOzw5WWCI7i93Crt2MA/ZEGTv+oVfH8vKXe1ZqyglUnoNAj0wGBLa/luz7SsXrH3DUo7vP6zoxk1cThkmwmPhVNd4GW+1orzyGxnWBQM8JRDpmz4pa36iaNasgyvEqfKjGEBJsg2pcveXvqU58gwG9xRPwcZMba62ogU1Gzt4GIK8fqm7XN3rCl4aIIa/CnXrgsVrPpjVBvxtxvQ32rS5M0HcXCtvbet1v0d2oOmnNqcqe/82aq20jErZ6GdQZY/29Yz843rH4Llf0Kl08ZoaFL/ZWW2NJG5McHdgZ3WeWUgVDa1a X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(346002)(396003)(376002)(136003)(39860400002)(230922051799003)(451199024)(186009)(64100799003)(82310400011)(1800799012)(46966006)(40470700004)(36840700001)(40460700003)(16526019)(107886003)(2616005)(26005)(8676002)(6666004)(426003)(336012)(82740400003)(8936002)(4326008)(86362001)(5660300002)(478600001)(316002)(70206006)(110136005)(54906003)(36860700001)(70586007)(83380400001)(356005)(7636003)(47076005)(41300700001)(2906002)(40480700001)(36756003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2023 15:51:30.7028 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81dbc293-8ee0-4dc1-dc1d-08dbf029e3bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6146 X-Patchwork-Delegate: kuba@kernel.org In controlled flood mode, for each bridge FID family (i.e., 802.1Q and 802.1D) and packet type (i.e., UUC/MC/BC), the hardware needs to be told which PGT address to use as the base address for the flood table and how to determine the offset from the base for each FID. The above is not needed in CFF mode where each FID has its own flood table instead of the FID family itself. Therefore, create a new FID family operation for the above configuration and only implement it for the 802.1Q and 802.1D families in controlled flood mode. No functional changes intended. Signed-off-by: Petr Machata Reviewed-by: Ido Schimmel --- .../net/ethernet/mellanox/mlxsw/spectrum_fid.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c index 0c7295d7e693..9ba4748e8d23 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c @@ -95,6 +95,8 @@ struct mlxsw_sp_fid_ops { const struct net_device *nve_dev); int (*vid_to_fid_rif_update)(const struct mlxsw_sp_fid *fid, const struct mlxsw_sp_rif *rif); + int (*flood_table_init)(struct mlxsw_sp_fid_family *fid_family, + const struct mlxsw_sp_flood_table *flood_table); }; struct mlxsw_sp_fid_family { @@ -1078,8 +1080,8 @@ mlxsw_sp_fid_8021d_vid_to_fid_rif_update(const struct mlxsw_sp_fid *fid, } static int -mlxsw_sp_fid_flood_table_init(struct mlxsw_sp_fid_family *fid_family, - const struct mlxsw_sp_flood_table *flood_table) +mlxsw_sp_fid_flood_table_init_ctl(struct mlxsw_sp_fid_family *fid_family, + const struct mlxsw_sp_flood_table *flood_table) { enum mlxsw_sp_flood_type packet_type = flood_table->packet_type; struct mlxsw_sp *mlxsw_sp = fid_family->mlxsw_sp; @@ -1121,6 +1123,7 @@ static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_8021d_ops_ctl = { .nve_flood_index_clear = mlxsw_sp_fid_8021d_nve_flood_index_clear, .fdb_clear_offload = mlxsw_sp_fid_8021d_fdb_clear_offload, .vid_to_fid_rif_update = mlxsw_sp_fid_8021d_vid_to_fid_rif_update, + .flood_table_init = mlxsw_sp_fid_flood_table_init_ctl, }; #define MLXSW_SP_FID_8021Q_MAX (VLAN_N_VID - 2) @@ -1462,6 +1465,7 @@ static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_8021q_ops_ctl = { .nve_flood_index_clear = mlxsw_sp_fid_8021d_nve_flood_index_clear, .fdb_clear_offload = mlxsw_sp_fid_8021q_fdb_clear_offload, .vid_to_fid_rif_update = mlxsw_sp_fid_8021q_vid_to_fid_rif_update, + .flood_table_init = mlxsw_sp_fid_flood_table_init_ctl, }; /* There are 4K-2 802.1Q FIDs */ @@ -1723,9 +1727,12 @@ mlxsw_sp_fid_flood_tables_init(struct mlxsw_sp_fid_family *fid_family) const struct mlxsw_sp_flood_table *flood_table; flood_table = &fid_family->flood_tables[i]; - err = mlxsw_sp_fid_flood_table_init(fid_family, flood_table); - if (err) - goto err_flood_table_init; + if (fid_family->ops->flood_table_init) { + err = fid_family->ops->flood_table_init(fid_family, + flood_table); + if (err) + goto err_flood_table_init; + } } return 0;