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Tsirkin" , Nicolin Chen , Niklas Schnelle , Shameerali Kolothum Thodi , Yi Liu , Keqian Zhu Subject: [PATCH v4 01/17] iommu: Add IOMMU_CAP_ENFORCE_CACHE_COHERENCY Date: Mon, 7 Nov 2022 20:48:54 -0400 Message-Id: <1-v4-0de2f6c78ed0+9d1-iommufd_jgg@nvidia.com> In-Reply-To: <0-v4-0de2f6c78ed0+9d1-iommufd_jgg@nvidia.com> References: X-ClientProxiedBy: BL1PR13CA0438.namprd13.prod.outlook.com (2603:10b6:208:2c3::23) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|BN9PR12MB5212:EE_ X-MS-Office365-Filtering-Correlation-Id: 9220ab46-6123-4676-b1b6-08dac1230cac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gKjIQnGMPRKtOkHsjW6aBRi88oQRYcLBX8Jv5Pl6MYpoiwH+WR5xEwh7UsZC5ck8SEkNGTZaaRlQhKK1VIKK31UaJc9pPwlSsRJTSHsnSQZQ6l9A+bJeho0yQzFbu75fsvHRn2NDJKCz5xhov4z225VAYM6Wz/aSdgpxXgXn8cURnopPvZSBNFI77ARghah3N/W/lHKuW/V/QwawvyaPVUuAuBJLCHMpxh3kNxvRcOoE3QOB9fXx0WcVmf3tJ05DRWz4lwPyOZcNLsQ8U3jeBWR0LXnC5wGT08Qv5ZBgFa74Eqga7mAenBucDLl9K/rZP5614Ua35r/P1RizPNL/TUrMhyqYSQUdVbGu2mR1X+CaBIjZLGZtqQLH4GT+gd2RrC3GdfgIA1ud4f3TkBUYmAygol45oJQcGQpWKi/v7iUzFpsfRKgNvV//S9VwR7HX4227XZUrzXkIK6somcYR4pFTa24JhJ9BongsCUOvGvPpvsVk3pgB3egzhG9R+OszJwKHbbGUJdg0X5jtlKlXeUScQWQ3pi123dH3gR/ce1wfakooB2PlOReQfxcse758Jiq9t1D1AQ4ESirfQij+FrKt3LAdCLbtcW+tdhvQ77HOH4JIa6lUSSB1kjF6ziPaS43GdDI2ocNTKof9w06wCbJAnbeau7NCqTLXievm7FEN1PoqTr1GouG4Uk4vwA1EPvH3Z8b0eNsBMUkzgH371cjM0MSxSoFnCYr0huf1hfmTCq+mM9oodS2lksTk/bbXNzEI+vbsp850UmUREmA7HA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(136003)(376002)(346002)(396003)(366004)(39860400002)(451199015)(83380400001)(36756003)(86362001)(478600001)(2906002)(6486002)(38100700002)(921005)(26005)(186003)(6512007)(2616005)(54906003)(316002)(4326008)(66476007)(6666004)(6506007)(110136005)(41300700001)(8676002)(8936002)(7416002)(7406005)(66946007)(66556008)(5660300002)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: uxamuUdY7ZMjMRqD7E/gr+S5zvHUeeuRabxEvwHHUuWa7X9oyPopm3Qg71wyE68fYjVZwghXQYRBgHQxCTP7NctKJ/EfgxfYNdDNo092u/eCvuEas9hpzJEdaEcFUBEUKnkkay1ovQNjbGvAICDeyKKx6WOC9cWVPWx/Kib3aW5YwHm1nMyvhNQIUqJm0xWkSW8ZhhsrE2Oca/zD4YhqSLHydezEJKtj2SbPorOySPih4VjRZhjHjKLEAn77sxWpVRmw26fSaLC6LJAUpxKk3oFZJOFbluwzDF5gxZ3wOuqKvTaMbxGtjwDtNV8NpF4Zl0CCI+grCYp4y8A2163+MY4b0yJgAq7vRrFUnMvzj9Kd89L6YhFanawbTA+jSRw0PdYkvuodt/86vXj/7IlnLpFY7qLBlEND7ynhcIPqiXrWPyg5+HCNudQGfxxKM9mzWwSvUCfhuApzPJfer6BvssAsW+sAnG28v2+MtkdPb4gP2420wlF9nJ/JPGRHTpgBLTqm/npXw48HXTGdFtpyki+kzXLK8vePwVg7bVlZjMxK/ipdzTl+w7WWRonOUqnqzl4Y+CHoCygnkua0p5rU7uBGaRAm1+TnIul/oGHrIwDi/jCu/ZiZSBiVqN6NkZqQAqOKiyWW/h8wuysDb/MOnQaOiSGETsxLUwW2xNsHmU3lxaLMVyx5t27pecp7ed4hHlsi9TfhorPWQ+0s4yKy9rq4o+9gAgUPv89SllYXe2eANj3gWK3uee/eWTMfZw2qteI5ODWopKfGaGb2eVZzWDX2X20fEI7q9uMTqYF298BlQzt+2rWFOrzU9L1ISmHT1J2kMhiqxaOIl9QM2j+z+P5XVTUKByCh8LAYF7CMhciouDVG8Giyx7tSDLU04V4lX1fOuvQ56tLyI3X1R+prxYHaRnCRKq1rA4jD5NMF2jikvXu7B9+Wq80m1yAW/WOjTRFgjT0vIjhCIBeaO4Uh8lU0MagLopcHSNE+uOUj6F+ZLKwuLejFKFy/1OeHnihbNp4EwKmfV7NgA5pLDwRcRtDa1gPeKClErDeurdmP4zEQ89kyD+eDZCpshshumg/9QMypN5yJ2ceWSx4qimoKB8xrOyOw2/85upMDNvqYF3PbitjA/f6o6k3SdlMtM/YpiUzIUaGNI+pRRu5c4Qx9q5C6+VAlITItuSYYjm9iOIUw38lYB03idg3q8vJMX3waB+YutBtImCT6S8+jVazdHC6ajQ3893hV0pKDfYqGlKzyy/5N0OkRtT1vsYSfAd/E1jv29cnayA3Sf85gK+U+iyuruzLxu6dv9Pn16lKYlwUpKsPVrt2xFRKakQTZps9S5GakCXLDzqUBQflbESww2SC0pwGkjaGe2BgYaVqVyUamfOCo7ihmMgngGxWq3/eVbInISJeKqE4Hl+fC/u+mstzmWlllL3JLSbujQufcJJQQqQXWEfFjyXqRty6jCkAYBVXYATYQKtui2aN9Dgqbd5G7XZkmvkUeywOhU7TGegru4Srys69y75I0lKkZCVvLvr3dJBYpr9N8n0wc8pOBFMRatI990naqnBixD7B8uJs= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9220ab46-6123-4676-b1b6-08dac1230cac X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Nov 2022 00:49:10.8726 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jnhGyQ8zMhg5IDP9+8K/SoG0O0So/whH8HxEkZ5N/NEPcAC+kkH19O35X2QvSREd X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5212 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org This queries if a domain linked to a device should expect to support enforce_cache_coherency() so iommufd can negotiate the rules for when a domain should be shared or not. For iommufd a device that declares IOMMU_CAP_ENFORCE_CACHE_COHERENCY will not be attached to a domain that does not support it. Reviewed-by: Lu Baolu Reviewed-by: Kevin Tian Tested-by: Nicolin Chen Signed-off-by: Jason Gunthorpe --- drivers/iommu/amd/iommu.c | 2 ++ drivers/iommu/intel/iommu.c | 16 +++++++++++----- include/linux/iommu.h | 5 +++++ 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 45299eb7e8e306..240c535e317cc7 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2278,6 +2278,8 @@ static bool amd_iommu_capable(struct device *dev, enum iommu_cap cap) return false; case IOMMU_CAP_PRE_BOOT_PROTECTION: return amdr_ivrs_remap_support; + case IOMMU_CAP_ENFORCE_CACHE_COHERENCY: + return true; default: break; } diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index f298e51d5aa67a..157c9727411076 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4450,14 +4450,20 @@ static bool intel_iommu_enforce_cache_coherency(struct iommu_domain *domain) static bool intel_iommu_capable(struct device *dev, enum iommu_cap cap) { - if (cap == IOMMU_CAP_CACHE_COHERENCY) + struct device_domain_info *info = dev_iommu_priv_get(dev); + + switch (cap) { + case IOMMU_CAP_CACHE_COHERENCY: return true; - if (cap == IOMMU_CAP_INTR_REMAP) + case IOMMU_CAP_INTR_REMAP: return irq_remapping_enabled == 1; - if (cap == IOMMU_CAP_PRE_BOOT_PROTECTION) + case IOMMU_CAP_PRE_BOOT_PROTECTION: return dmar_platform_optin(); - - return false; + case IOMMU_CAP_ENFORCE_CACHE_COHERENCY: + return ecap_sc_support(info->iommu->ecap); + default: + return false; + } } static struct iommu_device *intel_iommu_probe_device(struct device *dev) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 68d7d304cdb761..a09fd32d8cc273 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -124,6 +124,11 @@ enum iommu_cap { IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */ IOMMU_CAP_PRE_BOOT_PROTECTION, /* Firmware says it used the IOMMU for DMA protection and we should too */ + /* + * Per-device flag indicating if enforce_cache_coherency() will work on + * this device. + */ + IOMMU_CAP_ENFORCE_CACHE_COHERENCY, }; /* These are the possible reserved region types */