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Tsirkin" , Nicolin Chen , Halil Pasic , Niklas Schnelle , Shameerali Kolothum Thodi , Yi Liu , Keqian Zhu Subject: [PATCH v5 01/19] iommu: Add IOMMU_CAP_ENFORCE_CACHE_COHERENCY Date: Wed, 16 Nov 2022 17:00:37 -0400 Message-Id: <1-v5-4001c2997bd0+30c-iommufd_jgg@nvidia.com> In-Reply-To: <0-v5-4001c2997bd0+30c-iommufd_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR07CA0018.namprd07.prod.outlook.com (2603:10b6:208:1a0::28) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH8PR12MB7136:EE_ X-MS-Office365-Filtering-Correlation-Id: 2f072615-b834-46e2-dd58-08dac815a9da X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LJ5pfMikALZwYO/Ba+2qxrfQCrpPpgfTi81j/x9rRabjLMks2YOcaK6mNSiVIPCIaazsTcNZ8lNaO6mVqsRk7DINLtt7uu57IXTX6RZX4aYJoqSRe4opCEERA2e3fNfMZiHtiJNojLD3aYqkjt7tTuyuWp4W2/FXniKm2cyCeZN4s412R2WzCDCHM1f+Mr2pvOBvldca2+13FLmiCYtqPqnlCQx0TOLTqaGBl5kg9uIcjE6ogmJ6uUHOiLiMxkLivLhw1EQyXFzwWbWg2eiG8aRBJjDCJ+LYhZUAHxm4MeX5z9FvcVb3c7FkkyPXX7kJELkn9xY+q+qvpgyQMuzQ9mxLXAMb8XEbAc3PiHyBQ20DhDlJId4U01lfGFvxCY7YrMY3gg2ZnCWYXEMgxepE/o0kWZIqteY9RZNYWYHy+Ksi/EWOG0fevMHgdaSxfo+otJ7ZqpIzDmgvw+4+vaB5drr95UxJGohIkK4iCkb6oMBBPPkFcuKm4q/QU2hGcEyFnoHrdntKPZyKKzDT9TxfrhUfCvhMPY4RQ1rNoVLL01XIU/ncTWtprYnY/SufNw0mypeaQsuAO5cE8LMSoFzZoae9oXlt1Qvquzr6rHulylqJSyFyilZrHN1cNQMNY/K4hEU9+VPP33O6tapa5nZhpuuaRZOgR/r1uBhZcyjundFi1zRcBQnNN/CTq+Yux9TONNbKmwgHQjfWb6iHBqAsCHqdSaGmjPJFUUa+w8R5Vp5vK337jenwV9aI5mj1CLClH2CMLsSLnMQRaXM8v/kwlw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(39860400002)(346002)(376002)(366004)(451199015)(36756003)(41300700001)(4326008)(8676002)(66556008)(6486002)(186003)(66476007)(86362001)(66946007)(2616005)(478600001)(26005)(316002)(6666004)(110136005)(54906003)(6506007)(921005)(6512007)(83380400001)(2906002)(7406005)(7416002)(8936002)(5660300002)(38100700002)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4lhDlAi+aZ/Q3Avj0eiYxz9Br5gCo0KJGNl+Ny4DZ+jyCxYW09GNSAb6yfkwYrgGKRoJBMNZAOJfmXZ/39cxr1LI7kvJEr4uBgJ1ZCqSdTPZ6o6RPvrUxlT9ePKeq/k3a4XVh6158R7XVEhIcfvTcmnJNuU0hOJr8JsEM4l45VdsKpi9620e5Ec64apRNoPczX/Cax56xmD4OBEXb0cCqEokzun+C3fVRrdgKZhi0em2SAbB5Bnzk/yehD5hKmmnvReg+n3+V2It2DTUhOmXHLAct+MNMNpk0IX58TUfz9G9ezqEAGB7f6Z6ZRVnaV1VXP/21ElaVYR3yVmYmMj7+7+WTYWbSp5GA3GFirpQLQdKdgEe+H5r7d4IpMz3zjLaiEDAxTQTGmYOzgn+wfFHGgd8PPaoJUd7B+qgxGUHNUzyQX3n3mAdhGXXTCp89xUZ1I4rLMsgnK9UKclDXonKdyMY3+3ZOSwwBZTQyBPReSKNl7E8eCbqH7Ynfl9Q+eR+wq4TvGX3pNmZHewTef+ie+Fe1mtTgRhOOYY8WtzI/JBiop+jK04sBs1mMwaDUej/X3OuDmmxLqoynH3CdO5vUHvfXsjYiuoI8rSsjl4sfHe9vVQMBpcUX4l3vnEUnpEb7mIwdTDk3rW21YmwO664s3DSASRlOloXPAMSxdKRBJtGVQxWCMgCL4N+Osj2amOv3fAZisj9S+uc+xe/ndyLLMKrTNpbz0+RNHiB2+eaNq0cPO4UdheWCsvZeSklkLFetEyIzKRFCNYxhfUHbHSLc1l2i41yyKvY0cTlx8hKVknqjt0OgpiaYwI4ZNvU//RJm61gKRLU7Y2t1q4szYu5P1J6DtZHM8YpFivFhQUDYR7UAtG/uIz6hXI7VIUN16q9i5oMcE3yxN3U3O7qD1tuewAtSEGnVB1RUswiqtcUmnLF1O4RfHeGVjFVXoffWKnBSLgLjxroefphMCJ1TLMBXTkpDjDkT6dPKxv5EE0rIE2M/Lj5me8IyZtEK9XICDNp94TtOdKTjTuzES3cHIGgS/XEaMAhNxKvj+kMhC4m77uu14Gy5XG9eu9+Wtjpce7OYUaNOeVpb7GsIfcxjlS06zTZjZieZ2uis69yTNZfwXM5CKjFDzTkgkVU/MLL/BPvZXIfiIyYs54BaoKvDuVQMhfhXrz3bSyD7nsW9OrCD3LitLsNRaxreIQnmwYKMaOPDJt9KpGNzz2OX7GQBEE3Ju5X4YvZSSqeVF8Pg5bk0XHcVTSyp9LQ/PhxhFbH+BN4P4xUCphM2tyLbtPoiFmfTQE5MixCxuQ3Int05cHGH9BBqaAFTomGgeJ8DSuDGqFC1BVnouDnOMrJ51KL5ZO01qkMzl+4j6yaxZz0vtxNGOR9DMIsL7ePbWwyQLspjwkeKBO1uSR467B8FWF5JL68CnHkBElKicMauRl+CYHFG86lFRdrZOK2x0c1UYrEv048z9eVEc6bCAB/0UWfUFYyZ4UnNIPCeedLCTeXhfXe542Q9BT2hxfwWA27I2VePLMQlh5rYVx0zFmsPgn+Zjh8DIgFE9UQ4wCfdZqRUsfd/dY= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2f072615-b834-46e2-dd58-08dac815a9da X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Nov 2022 21:00:59.9500 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: FcnOxbvzt3HOrZWyBDfqvH6vdeBnjwZDGJ+W3ckvA4TnmIoz9ye9n04hdm8jjhSb X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7136 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org This queries if a domain linked to a device should expect to support enforce_cache_coherency() so iommufd can negotiate the rules for when a domain should be shared or not. For iommufd a device that declares IOMMU_CAP_ENFORCE_CACHE_COHERENCY will not be attached to a domain that does not support it. Reviewed-by: Lu Baolu Reviewed-by: Kevin Tian Tested-by: Nicolin Chen Tested-by: Yi Liu Tested-by: Lixiao Yang Tested-by: Matthew Rosato Signed-off-by: Jason Gunthorpe --- drivers/iommu/amd/iommu.c | 2 ++ drivers/iommu/intel/iommu.c | 16 +++++++++++----- include/linux/iommu.h | 5 +++++ 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 45299eb7e8e306..240c535e317cc7 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2278,6 +2278,8 @@ static bool amd_iommu_capable(struct device *dev, enum iommu_cap cap) return false; case IOMMU_CAP_PRE_BOOT_PROTECTION: return amdr_ivrs_remap_support; + case IOMMU_CAP_ENFORCE_CACHE_COHERENCY: + return true; default: break; } diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index f298e51d5aa67a..157c9727411076 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4450,14 +4450,20 @@ static bool intel_iommu_enforce_cache_coherency(struct iommu_domain *domain) static bool intel_iommu_capable(struct device *dev, enum iommu_cap cap) { - if (cap == IOMMU_CAP_CACHE_COHERENCY) + struct device_domain_info *info = dev_iommu_priv_get(dev); + + switch (cap) { + case IOMMU_CAP_CACHE_COHERENCY: return true; - if (cap == IOMMU_CAP_INTR_REMAP) + case IOMMU_CAP_INTR_REMAP: return irq_remapping_enabled == 1; - if (cap == IOMMU_CAP_PRE_BOOT_PROTECTION) + case IOMMU_CAP_PRE_BOOT_PROTECTION: return dmar_platform_optin(); - - return false; + case IOMMU_CAP_ENFORCE_CACHE_COHERENCY: + return ecap_sc_support(info->iommu->ecap); + default: + return false; + } } static struct iommu_device *intel_iommu_probe_device(struct device *dev) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 68d7d304cdb761..a09fd32d8cc273 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -124,6 +124,11 @@ enum iommu_cap { IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */ IOMMU_CAP_PRE_BOOT_PROTECTION, /* Firmware says it used the IOMMU for DMA protection and we should too */ + /* + * Per-device flag indicating if enforce_cache_coherency() will work on + * this device. + */ + IOMMU_CAP_ENFORCE_CACHE_COHERENCY, }; /* These are the possible reserved region types */