| Message ID | 1569290b21cc787a424469ed74456a7e976b102d.1715084326.git.daniel@makrotopia.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | cc349b0771dccebf0fa9f5e1822ac444aef11448 |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [v2] dt-bindings: net: mediatek: remove wrongly added clocks and SerDes | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Not a local patch |
On 07/05/2024 14:20, Daniel Golle wrote: > Several clocks as well as both sgmiisys phandles were added by mistake > to the Ethernet bindings for MT7988. Also, the total number of clocks > didn't match with the actual number of items listed. > > This happened because the vendor driver which served as a reference uses > a high number of syscon phandles to access various parts of the SoC > which wasn't acceptable upstream. Hence several parts which have never > previously been supported (such SerDes PHY and USXGMII PCS) are going to > be implemented by separate drivers. As a result the device tree will > look much more sane. > > Quickly align the bindings with the upcoming reality of the drivers > actually adding support for the remaining Ethernet-related features of > the MT7988 SoC. > > Fixes: c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding") > Signed-off-by: Daniel Golle <daniel@makrotopia.org> > --- > v2: don't make changes to the order of clocks Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
Hello: This patch was applied to netdev/net.git (main) by Jakub Kicinski <kuba@kernel.org>: On Tue, 7 May 2024 13:20:43 +0100 you wrote: > Several clocks as well as both sgmiisys phandles were added by mistake > to the Ethernet bindings for MT7988. Also, the total number of clocks > didn't match with the actual number of items listed. > > This happened because the vendor driver which served as a reference uses > a high number of syscon phandles to access various parts of the SoC > which wasn't acceptable upstream. Hence several parts which have never > previously been supported (such SerDes PHY and USXGMII PCS) are going to > be implemented by separate drivers. As a result the device tree will > look much more sane. > > [...] Here is the summary with links: - [v2] dt-bindings: net: mediatek: remove wrongly added clocks and SerDes https://git.kernel.org/netdev/net/c/cc349b0771dc You are awesome, thank you!
diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml index e74502a0afe8..3202dc7967c5 100644 --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml @@ -337,8 +337,8 @@ allOf: minItems: 4 clocks: - minItems: 34 - maxItems: 34 + minItems: 24 + maxItems: 24 clock-names: items: @@ -351,18 +351,6 @@ allOf: - const: ethwarp_wocpu1 - const: ethwarp_wocpu0 - const: esw - - const: netsys0 - - const: netsys1 - - const: sgmii_tx250m - - const: sgmii_rx250m - - const: sgmii2_tx250m - - const: sgmii2_rx250m - - const: top_usxgmii0_sel - - const: top_usxgmii1_sel - - const: top_sgm0_sel - - const: top_sgm1_sel - - const: top_xfi_phy0_xtal_sel - - const: top_xfi_phy1_xtal_sel - const: top_eth_gmii_sel - const: top_eth_refck_50m_sel - const: top_eth_sys_200m_sel @@ -375,16 +363,10 @@ allOf: - const: top_netsys_sync_250m_sel - const: top_netsys_ppefb_250m_sel - const: top_netsys_warp_sel - - const: wocpu1 - - const: wocpu0 - const: xgp1 - const: xgp2 - const: xgp3 - mediatek,sgmiisys: - minItems: 2 - maxItems: 2 - patternProperties: "^mac@[0-1]$": type: object
Several clocks as well as both sgmiisys phandles were added by mistake to the Ethernet bindings for MT7988. Also, the total number of clocks didn't match with the actual number of items listed. This happened because the vendor driver which served as a reference uses a high number of syscon phandles to access various parts of the SoC which wasn't acceptable upstream. Hence several parts which have never previously been supported (such SerDes PHY and USXGMII PCS) are going to be implemented by separate drivers. As a result the device tree will look much more sane. Quickly align the bindings with the upcoming reality of the drivers actually adding support for the remaining Ethernet-related features of the MT7988 SoC. Fixes: c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding") Signed-off-by: Daniel Golle <daniel@makrotopia.org> --- v2: don't make changes to the order of clocks .../devicetree/bindings/net/mediatek,net.yaml | 22 ++----------------- 1 file changed, 2 insertions(+), 20 deletions(-)