@@ -829,6 +829,7 @@
#define MSS_THRESHOLD_STOP 768
#define MSS_THRESHOLD_START 1024
+#define MSS_FC_MAX_TIMEOUT 5000
/* RX buffer constants */
#define MVPP2_SKB_SHINFO_SIZE \
@@ -946,6 +946,34 @@ void mvpp2_bm_pool_update_fc(struct mvpp2_port *port,
spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
}
+static int mvpp2_enable_global_fc(struct mvpp2 *priv)
+{
+ int val, timeout = 0;
+
+ /* Enable global flow control. In this stage global
+ * flow control enabled, but still disabled per port.
+ */
+ val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
+ val |= FLOW_CONTROL_ENABLE_BIT;
+ mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
+
+ /* Check if Firmware running and disable FC if not*/
+ val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
+ mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
+
+ while (timeout < MSS_FC_MAX_TIMEOUT) {
+ val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
+
+ if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT))
+ return 0;
+ usleep_range(10, 20);
+ timeout++;
+ }
+
+ priv->global_tx_fc = false;
+ return -EOPNOTSUPP;
+}
+
/* Release buffer to BM */
static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
dma_addr_t buf_dma_addr,
@@ -7307,7 +7335,7 @@ static int mvpp2_probe(struct platform_device *pdev)
struct resource *res;
void __iomem *base;
int i, shared;
- int err, val;
+ int err;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -7533,13 +7561,10 @@ static int mvpp2_probe(struct platform_device *pdev)
goto err_port_probe;
}
- /* Enable global flow control. In this stage global
- * flow control enabled, but still disabled per port.
- */
if (priv->global_tx_fc && priv->hw_version != MVPP21) {
- val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
- val |= FLOW_CONTROL_ENABLE_BIT;
- mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
+ err = mvpp2_enable_global_fc(priv);
+ if (err)
+ dev_warn(&pdev->dev, "CM3 firmware not running, TX FC disabled\n");
}
mvpp2_dbgfs_init(priv, pdev->name);