From patchwork Sun Jan 10 15:30:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Chulski X-Patchwork-Id: 12009259 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C213C433E6 for ; Sun, 10 Jan 2021 15:35:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 009162343F for ; Sun, 10 Jan 2021 15:35:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727332AbhAJPfC (ORCPT ); Sun, 10 Jan 2021 10:35:02 -0500 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:17690 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727175AbhAJPe6 (ORCPT ); Sun, 10 Jan 2021 10:34:58 -0500 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 10AFPV9T022752; Sun, 10 Jan 2021 07:32:11 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=ncb9QbrBugW37aDFKBIROi0JWgSAf8S9BmfsOxURfXI=; b=PJfr1G8JcX8rhQm3s13Pja2U+NwbIo14e12u/dQsYE1XyUjz0zWDrDQoLkn8DzYbqdq3 m3zrRsNvmMuZO0E67CpOpTwPVtT7hjuT5zrHi7u8zJ2LBQVgbMbCqaNs9Y6IdzbsBXpZ mt0BOkxQjOnI5wscnsw5cHhS0I0ThHdDpQYDwGh6bGtKT4X00PnfNCCDYYiOpJYP8oZZ mgBHNMuPEYfVsLSCR75CINouLUbfUnedegPVPphtzbhqLQuUwcyYP/88qkNbovJWUQoo YYu8J/nj850fV7kmkUjxJzDFas1rSQlR73X4zMcfP9ELEPlmm1ptNGX8am22mGR30ewc ZQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 35ycvphvf3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 10 Jan 2021 07:32:11 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 10 Jan 2021 07:32:09 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 10 Jan 2021 07:32:08 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 10 Jan 2021 07:32:08 -0800 Received: from stefan-pc.marvell.com (stefan-pc.marvell.com [10.5.25.21]) by maili.marvell.com (Postfix) with ESMTP id B7FAD3F703F; Sun, 10 Jan 2021 07:32:05 -0800 (PST) From: To: CC: , , , , , , , , , , , Subject: [PATCH RFC net-next 19/19] net: mvpp2: add TX FC firmware check Date: Sun, 10 Jan 2021 17:30:23 +0200 Message-ID: <1610292623-15564-20-git-send-email-stefanc@marvell.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1610292623-15564-1-git-send-email-stefanc@marvell.com> References: <1610292623-15564-1-git-send-email-stefanc@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343,18.0.737 definitions=2021-01-09_13:2021-01-07,2021-01-09 signatures=0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC From: Stefan Chulski Patch check that TX FC firmware is running in CM3. If not, global TX FC would be disabled. Signed-off-by: Stefan Chulski --- drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 + drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 39 ++++++++++++++++---- 2 files changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h index 3451618..1a65f2c 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h @@ -829,6 +829,7 @@ #define MSS_THRESHOLD_STOP 768 #define MSS_THRESHOLD_START 1024 +#define MSS_FC_MAX_TIMEOUT 5000 /* RX buffer constants */ #define MVPP2_SKB_SHINFO_SIZE \ diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index 3607382..1690142 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -946,6 +946,34 @@ void mvpp2_bm_pool_update_fc(struct mvpp2_port *port, spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); } +static int mvpp2_enable_global_fc(struct mvpp2 *priv) +{ + int val, timeout = 0; + + /* Enable global flow control. In this stage global + * flow control enabled, but still disabled per port. + */ + val = mvpp2_cm3_read(priv, MSS_FC_COM_REG); + val |= FLOW_CONTROL_ENABLE_BIT; + mvpp2_cm3_write(priv, MSS_FC_COM_REG, val); + + /* Check if Firmware running and disable FC if not*/ + val |= FLOW_CONTROL_UPDATE_COMMAND_BIT; + mvpp2_cm3_write(priv, MSS_FC_COM_REG, val); + + while (timeout < MSS_FC_MAX_TIMEOUT) { + val = mvpp2_cm3_read(priv, MSS_FC_COM_REG); + + if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT)) + return 0; + usleep_range(10, 20); + timeout++; + } + + priv->global_tx_fc = false; + return -EOPNOTSUPP; +} + /* Release buffer to BM */ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, dma_addr_t buf_dma_addr, @@ -7307,7 +7335,7 @@ static int mvpp2_probe(struct platform_device *pdev) struct resource *res; void __iomem *base; int i, shared; - int err, val; + int err; priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -7533,13 +7561,10 @@ static int mvpp2_probe(struct platform_device *pdev) goto err_port_probe; } - /* Enable global flow control. In this stage global - * flow control enabled, but still disabled per port. - */ if (priv->global_tx_fc && priv->hw_version != MVPP21) { - val = mvpp2_cm3_read(priv, MSS_FC_COM_REG); - val |= FLOW_CONTROL_ENABLE_BIT; - mvpp2_cm3_write(priv, MSS_FC_COM_REG, val); + err = mvpp2_enable_global_fc(priv); + if (err) + dev_warn(&pdev->dev, "CM3 firmware not running, TX FC disabled\n"); } mvpp2_dbgfs_init(priv, pdev->name);