From patchwork Sun Jan 24 11:44:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Chulski X-Patchwork-Id: 12042263 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53074C433DB for ; Sun, 24 Jan 2021 11:49:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1C31723100 for ; Sun, 24 Jan 2021 11:49:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726880AbhAXLte (ORCPT ); Sun, 24 Jan 2021 06:49:34 -0500 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:62480 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726825AbhAXLse (ORCPT ); Sun, 24 Jan 2021 06:48:34 -0500 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 10OBjl09027030; Sun, 24 Jan 2021 03:45:47 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=DRNeBObxaTv+NaHVOddRigbW7rCjKNCowIE+2LC5M/Y=; b=gIFZfGU5QqpKEmEqogVyEV6LO+jQcB4xVA052Na+SCw7YWR4wa/EUyZaZwNAV4YVK6Ws pjjdVeyq6ILcVJefYlcbaR/+OJ4tRPpF8IHZF4npSJsxT3V4xlIDpRDANJhiLgnLIIiP CwPeLwfuzPGJNxBoZnhXwDywQSWo52Sm3Pm/sA7HNHwPjoi57hADc5yd5b3PVlxdx8eA wVBVK8R+gf7N1TkvzHbI33hjAC2OdnAC6yt09OOyhPImKFGN0PX0DO8/ptbCstMGFI89 i4UxPu7Eu/1bds0gSvEbvVoK77zbBUqxiia4ad97W8TnjuBbQR3/490fYl5oDT1Si3xV vw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 368m6u9suy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 24 Jan 2021 03:45:47 -0800 Received: from SC-EXCH03.marvell.com (10.93.176.83) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 24 Jan 2021 03:45:45 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 24 Jan 2021 03:45:44 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 24 Jan 2021 03:45:45 -0800 Received: from stefan-pc.marvell.com (stefan-pc.marvell.com [10.5.25.21]) by maili.marvell.com (Postfix) with ESMTP id 05F243F7041; Sun, 24 Jan 2021 03:45:41 -0800 (PST) From: To: CC: , , , , , , , , , , , Subject: [PATCH v2 RFC net-next 18/18] net: mvpp2: add TX FC firmware check Date: Sun, 24 Jan 2021 13:44:07 +0200 Message-ID: <1611488647-12478-19-git-send-email-stefanc@marvell.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1611488647-12478-1-git-send-email-stefanc@marvell.com> References: <1611488647-12478-1-git-send-email-stefanc@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343,18.0.737 definitions=2021-01-24_04:2021-01-22,2021-01-24 signatures=0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC From: Stefan Chulski Patch check that TX FC firmware is running in CM3. If not, global TX FC would be disabled. Signed-off-by: Stefan Chulski --- drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 + drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 41 ++++++++++++++++---- 2 files changed, 35 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h index 417cc43..40aad0c 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h @@ -829,6 +829,7 @@ #define MSS_THRESHOLD_STOP 768 #define MSS_THRESHOLD_START 1024 +#define MSS_FC_MAX_TIMEOUT 5000 /* RX buffer constants */ #define MVPP2_SKB_SHINFO_SIZE \ diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index f8fc682..69157e8 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -934,6 +934,34 @@ static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port, spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); } +static int mvpp2_enable_global_fc(struct mvpp2 *priv) +{ + int val, timeout = 0; + + /* Enable global flow control. In this stage global + * flow control enabled, but still disabled per port. + */ + val = mvpp2_cm3_read(priv, MSS_FC_COM_REG); + val |= FLOW_CONTROL_ENABLE_BIT; + mvpp2_cm3_write(priv, MSS_FC_COM_REG, val); + + /* Check if Firmware running and disable FC if not*/ + val |= FLOW_CONTROL_UPDATE_COMMAND_BIT; + mvpp2_cm3_write(priv, MSS_FC_COM_REG, val); + + while (timeout < MSS_FC_MAX_TIMEOUT) { + val = mvpp2_cm3_read(priv, MSS_FC_COM_REG); + + if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT)) + return 0; + usleep_range(10, 20); + timeout++; + } + + priv->global_tx_fc = false; + return -EOPNOTSUPP; +} + /* Release buffer to BM */ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, dma_addr_t buf_dma_addr, @@ -7289,7 +7317,7 @@ static int mvpp2_probe(struct platform_device *pdev) struct resource *res; void __iomem *base; int i, shared; - int err, val; + int err; priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -7517,13 +7545,12 @@ static int mvpp2_probe(struct platform_device *pdev) goto err_port_probe; } - /* Enable global flow control. In this stage global - * flow control enabled, but still disabled per port. - */ if (priv->global_tx_fc && priv->hw_version != MVPP21) { - val = mvpp2_cm3_read(priv, MSS_FC_COM_REG); - val |= FLOW_CONTROL_ENABLE_BIT; - mvpp2_cm3_write(priv, MSS_FC_COM_REG, val); + err = mvpp2_enable_global_fc(priv); + if (err) { + dev_warn(&pdev->dev, "CM3 firmware not running, version should be higher than 18.09\n"); + dev_warn(&pdev->dev, "Flow control not supported\n"); + } } mvpp2_dbgfs_init(priv, pdev->name);