diff mbox series

[3/3] arm64: dts: imx93: add flexcan nodes

Message ID 1669116752-4260-3-git-send-email-haibo.chen@nxp.com (mailing list archive)
State Awaiting Upstream
Delegated to: Netdev Maintainers
Headers show
Series [1/3] can: flexcan: add auto stop mode for IMX93 to support wakeup | expand

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netdev/header_inline success No static functions without inline keyword in header files
netdev/build_32bit success Errors and warnings before: 0 this patch: 0
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netdev/build_clang success Errors and warnings before: 0 this patch: 0
netdev/module_param success Was 0 now: 0
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netdev/check_selftest success No net selftest shell script
netdev/verify_fixes success No Fixes tag
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Commit Message

Bough Chen Nov. 22, 2022, 11:32 a.m. UTC 
From: Haibo Chen <haibo.chen@nxp.com>

Add flexcan1 and flexcan2 nodes.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx93.dtsi | 28 ++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

Comments

Marc Kleine-Budde Nov. 24, 2022, 2:43 p.m. UTC | #1 
Shawn,

do you take this patch?

Marc

On 22.11.2022 19:32:32, haibo.chen@nxp.com wrote:
> From: Haibo Chen <haibo.chen@nxp.com>
> 
> Add flexcan1 and flexcan2 nodes.
> 
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx93.dtsi | 28 ++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
> index 5d79663b3b84..6808321ed809 100644
> --- a/arch/arm64/boot/dts/freescale/imx93.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
> @@ -223,6 +223,20 @@ lpuart2: serial@44390000 {
>  				status = "disabled";
>  			};
>  
> +			flexcan1: can@443a0000 {
> +				compatible = "fsl,imx93-flexcan";
> +				reg = <0x443a0000 0x10000>;
> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX93_CLK_BUS_AON>,
> +					 <&clk IMX93_CLK_CAN1_GATE>;
> +				clock-names = "ipg", "per";
> +				assigned-clocks = <&clk IMX93_CLK_CAN1>;
> +				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
> +				assigned-clock-rates = <40000000>;
> +				fsl,clk-source = /bits/ 8 <0>;
> +				status = "disabled";
> +			};
> +
>  			iomuxc: pinctrl@443c0000 {
>  				compatible = "fsl,imx93-iomuxc";
>  				reg = <0x443c0000 0x10000>;
> @@ -393,6 +407,20 @@ lpuart6: serial@425a0000 {
>  				status = "disabled";
>  			};
>  
> +			flexcan2: can@425b0000 {
> +				compatible = "fsl,imx93-flexcan";
> +				reg = <0x425b0000 0x10000>;
> +				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
> +					 <&clk IMX93_CLK_CAN2_GATE>;
> +				clock-names = "ipg", "per";
> +				assigned-clocks = <&clk IMX93_CLK_CAN2>;
> +				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
> +				assigned-clock-rates = <40000000>;
> +				fsl,clk-source = /bits/ 8 <0>;
> +				status = "disabled";
> +			};
> +
>  			lpuart7: serial@42690000 {
>  				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
>  				reg = <0x42690000 0x1000>;
> -- 
> 2.34.1
> 
>
Shawn Guo Dec. 31, 2022, 7:24 a.m. UTC | #2 
On Tue, Nov 22, 2022 at 07:32:32PM +0800, haibo.chen@nxp.com wrote:
> From: Haibo Chen <haibo.chen@nxp.com>
> 
> Add flexcan1 and flexcan2 nodes.
> 
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

Applied, thanks!
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
index 5d79663b3b84..6808321ed809 100644
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -223,6 +223,20 @@  lpuart2: serial@44390000 {
 				status = "disabled";
 			};
 
+			flexcan1: can@443a0000 {
+				compatible = "fsl,imx93-flexcan";
+				reg = <0x443a0000 0x10000>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_BUS_AON>,
+					 <&clk IMX93_CLK_CAN1_GATE>;
+				clock-names = "ipg", "per";
+				assigned-clocks = <&clk IMX93_CLK_CAN1>;
+				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+				assigned-clock-rates = <40000000>;
+				fsl,clk-source = /bits/ 8 <0>;
+				status = "disabled";
+			};
+
 			iomuxc: pinctrl@443c0000 {
 				compatible = "fsl,imx93-iomuxc";
 				reg = <0x443c0000 0x10000>;
@@ -393,6 +407,20 @@  lpuart6: serial@425a0000 {
 				status = "disabled";
 			};
 
+			flexcan2: can@425b0000 {
+				compatible = "fsl,imx93-flexcan";
+				reg = <0x425b0000 0x10000>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
+					 <&clk IMX93_CLK_CAN2_GATE>;
+				clock-names = "ipg", "per";
+				assigned-clocks = <&clk IMX93_CLK_CAN2>;
+				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+				assigned-clock-rates = <40000000>;
+				fsl,clk-source = /bits/ 8 <0>;
+				status = "disabled";
+			};
+
 			lpuart7: serial@42690000 {
 				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 				reg = <0x42690000 0x1000>;