From patchwork Mon Mar 18 09:29:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Subbaraya Sundeep X-Patchwork-Id: 13595110 X-Patchwork-Delegate: kuba@kernel.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2B5536122; Mon, 18 Mar 2024 09:30:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710754235; cv=none; b=gEyW1TWcBqaf7tM780zEy9hsOtNCROhuNutb1K2W9nRZkR8cmbsnjTegRmKZ//SU/HgY27BIieX3BlCur9IHeCEdfCTMMsTOWNu7ZxbEQOPE9sRnm9eNjE9F9ixI/sRuaMQAkeq30X24zfT1V6hdC9lYBydZjdnYmLWFfVntgac= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710754235; c=relaxed/simple; bh=4Hb9jbRlWYeyKViYjaod8C19ssNo3mf3yKVNdmOioug=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kLxdF3f1S637G+NRndrkoJYH8KcuCucazPZuW03TgQHgaLGvnWgYV3HNnjqheVLdixuqL9As9lCOH7TSoXAJj4GAQ0pYauTXQLcQjHblwos4teCe6ckybrNXTp57DGJ+3ns072PQ7EfInaAoixTyNkddgNdB6gtNGYIVx+GeUQU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=hJbvuCoc; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="hJbvuCoc" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42HMo2A9006638; Mon, 18 Mar 2024 02:30:28 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=pfpt0220; bh=NmmQRCZi034beJqnDhaoi G0ejgZQ2JEiKFCBg3EUDWg=; b=hJbvuCocV4Pa+JUaFDCtJ8O9oUF3c6ozSrGMa wXoLodntsor4DXg5xrOi9+g4sLNbDL80PWYj5tzGulSY9oPADEr4UfrxoVC1YxRJ pS8hOn9YRz+bbXqHVNvSveCz7L//5ouP3UvULH5/FZfah73POkycD32O7faZWhky bFgyG+G6//jwLnifEj/ojVTf/QoFWbYffz5qYSN125TUGN/e8nR9ezmsk/Afv9mt Tk1I9oJcFo+z5xkXEM1kxXFGBBsthWtQZ8/FtvO+ARsGQgKX+AP80FHmHoSgmuCF 2LdJpVoLyxN9RdPgqn2A68z/qgGQl7+wexQAQvkMgV8mDlKAg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3ww8skmj1x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 Mar 2024 02:30:28 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 18 Mar 2024 02:30:27 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 18 Mar 2024 02:30:27 -0700 Received: from hyd1358.marvell.com (unknown [10.29.37.11]) by maili.marvell.com (Postfix) with ESMTP id 6CC4C3F7065; Mon, 18 Mar 2024 02:30:23 -0700 (PDT) From: Subbaraya Sundeep To: , CC: , , , , , , , , , , Subbaraya Sundeep Subject: [v2 net PATCH 5/5] octeontx2-af: Use separate handlers for interrupts Date: Mon, 18 Mar 2024 14:59:58 +0530 Message-ID: <1710754198-18632-6-git-send-email-sbhatta@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1710754198-18632-1-git-send-email-sbhatta@marvell.com> References: <1710754198-18632-1-git-send-email-sbhatta@marvell.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: bHF1t9cbSMJa_0ko5trC-zXsGEmGBAlz X-Proofpoint-GUID: bHF1t9cbSMJa_0ko5trC-zXsGEmGBAlz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-17_12,2024-03-18_01,2023-05-22_02 X-Patchwork-Delegate: kuba@kernel.org For PF to AF interrupt vector and VF to AF vector same interrupt handler is registered which is causing race condition. When two interrupts are raised to two CPUs at same time then two cores serve same event corrupting the data. Fixes: 7304ac4567bc ("octeontx2-af: Add mailbox IRQ and msg handlers") Signed-off-by: Subbaraya Sundeep --- drivers/net/ethernet/marvell/octeontx2/af/rvu.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c index 0b65a18..ff78251 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c @@ -2533,10 +2533,9 @@ static void rvu_queue_work(struct mbox_wq_info *mw, int first, } } -static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) +static irqreturn_t rvu_mbox_pf_intr_handler(int irq, void *rvu_irq) { struct rvu *rvu = (struct rvu *)rvu_irq; - int vfs = rvu->vfs; u64 intr; intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); @@ -2550,6 +2549,18 @@ static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); + return IRQ_HANDLED; +} + +static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) +{ + struct rvu *rvu = (struct rvu *)rvu_irq; + int vfs = rvu->vfs; + u64 intr; + + /* Sync with mbox memory region */ + rmb(); + /* Handle VF interrupts */ if (vfs > 64) { intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); @@ -2894,7 +2905,7 @@ static int rvu_register_interrupts(struct rvu *rvu) /* Register mailbox interrupt handler */ sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), - rvu_mbox_intr_handler, 0, + rvu_mbox_pf_intr_handler, 0, &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); if (ret) { dev_err(rvu->dev,