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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn CC: Gal Pressman , Mark Bloch , "Moshe Shemesh" , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , "Jonathan Corbet" , , , , , Yael Chemla Subject: [PATCH net-next 3/4] net/mlx5e: Get counter group size by FW capability Date: Thu, 13 Mar 2025 21:24:45 +0200 Message-ID: <1741893886-188294-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1741893886-188294-1-git-send-email-tariqt@nvidia.com> References: <1741893886-188294-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E1:EE_|MN0PR12MB6248:EE_ X-MS-Office365-Filtering-Correlation-Id: 026ae6c9-0259-4091-8baa-08dd6264de09 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: zTc7to10CBFRt3aYDv0o1U/EuaPwBNiNFQqMp1disMxk5DTVl7flgFVAaZ8cxKLl23p96Kbls1JiKBk6QIMF81DVHgvf0bsbaPtvPhaE6ZoVuepuLfSVqNQYIL4ipTggbbd40DAXOhk2QDROqu/hi1IOs5CNVMEAJqEVKSpefnniTSaTurn1yj6wfq4gYBIWKYCyzKcG/I5b+KYR3febzDkCnYxnUQWkBwdIMGHAXOzsb3G+/gZSdSU25/FL6o7/OfgKlZRSaj12uT4hQEryFBtWCEzuz3Zn9sPNGra12kAb4EVOUhBaDoXcpxhK5KzlEEgkzRssZNs5ImL5p4pgh0xieO6nkrzoLLx+f20oicU3glqLLn87hIHXH+FeD5YYSopDYayUCwlq7YpqghEG9ArxHXpUgS/BcVRYeFDZ6grENCRbSuP2qskjdOEOUaARenb1AXksB8Co1MdvOf80A2LzQUkzUq0UhGBDxdsDpo2c8f2jWIerawD0cX/flBtNfJ+V/dq1MYUnqVbwYKYq0jiMs3lcT+bglylAHZ+fub5AvXQWoA1FJs4tnUMA34/kReBmGGw2O0vH+O6DsCiF/XxsXcgArExxnj5wrFDZ7CJ9E8Zr0wCTZn5N/4XYkP/J+7v/j6EfiLFoC0EfcBw/txPa83VmnnJpiAl1yQ41LBOIxhgpcDuKzQ27v+95u8SjKeRy2bf1xfIIWf4PY2lxGyWNdBoqAS/TDBD16VsBiAX9aXJUInIlkR6z104Y1NOazqxVCkbX30SQjxoCrTR3ibZ5BD7S8+4t1O8MomZb/k8/RhBtyRxGsNWGGp7mmnidLVeqzqwlPjxWR3ERi95vkxVIN3EOGf+1G7ckgKhFn50m3kd6DDmCTI55tOP6Am64m6HcXrqEz/eiRcdwenlCQddx/jvaFOr0hTH/AiFZVmXvKtA2q+nm7c44BAxlqTE/bBM4IxA3dvfqHT3itHr+nV20U87PR9kSszWfY2M7wMmCZhaNmmcwJADdURUMbHZs0RlJHEtZb1nxqbXJz3p4zxpbOSXmyRqj+yKuqGrepyvYD1XNWycnmmj27YwO2A7nkk/eP/VDhyM89LjpwEUIr0eDHgZVKkYTg29J/6OOcu9gRRGA7ZsF2Q03UbtgFX2tI2vUweKdDJovXvjieoDXIS4/xtzx9KA0HMQPRmokcuqS5qZ79NnIz9dDflQTdXWjyW8kOpBAIA/vV4iFbInbz1npP7XrgLMEKVIwEUCz/t3QMxZsMLwP/QRHiSvw+gl3hjOFOhNb5hvFRhCeGmUPaRu/T0yCOoNs5ydKRw4Dk7auphFDJrOv+yCYiUF2I7J7R1rER1kfT9bzCyQ9T+W7g0XPeHA3FSTZk5vGv8Zpy5alHcT8ln4y6PlNgLgmbgMdmk9RN41WwNgglVe5dUqv4lj1sPjAyo8gWgDpX5HkC2hbPviPxVO2YzaN77dGFo+iyAQ2AJftrRMK0RP6VaxqeA== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2025 19:25:51.5866 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 026ae6c9-0259-4091-8baa-08dd6264de09 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6248 X-Patchwork-Delegate: kuba@kernel.org From: Yael Chemla Retrieve the number of fields supported by each PPCNT counter group based on the FW capability for this group. Signed-off-by: Yael Chemla Signed-off-by: Tariq Toukan Reviewed-by: Kalesh AP --- .../ethernet/mellanox/mlx5/core/en_stats.c | 58 ++++++++++--------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c index 0cf0c920532f..a417962acfa9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -1257,6 +1257,13 @@ pport_phy_statistical_err_lanes_stats_desc[] = { #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS \ ARRAY_SIZE(pport_phy_statistical_err_lanes_stats_desc) +#define NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(dev) \ + (MLX5_CAP_PCAM_FEATURE(dev, ppcnt_statistical_group) ? \ + NUM_PPORT_PHY_STATISTICAL_COUNTERS : 0) +#define NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(dev) \ + (MLX5_CAP_PCAM_FEATURE(dev, per_lane_error_counters) ? \ + NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0) + static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) { struct mlx5_core_dev *mdev = priv->mdev; @@ -1264,11 +1271,9 @@ static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) num_stats = NUM_PPORT_PHY_LAYER_COUNTERS; - num_stats += MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) ? - NUM_PPORT_PHY_STATISTICAL_COUNTERS : 0; + num_stats += NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(mdev); - num_stats += MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters) ? - NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0; + num_stats += NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(mdev); return num_stats; } @@ -1281,14 +1286,15 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy) for (i = 0; i < NUM_PPORT_PHY_LAYER_COUNTERS; i++) ethtool_puts(data, pport_phy_layer_cntrs_stats_desc[i].format); - if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) - for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) - ethtool_puts(data, pport_phy_statistical_stats_desc[i].format); + for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(mdev); i++) + ethtool_puts(data, pport_phy_statistical_stats_desc[i].format); - if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) - for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++) - ethtool_puts(data, - pport_phy_statistical_err_lanes_stats_desc[i].format); + for (i = 0; + i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(mdev); + i++) + ethtool_puts(data, + pport_phy_statistical_err_lanes_stats_desc[i] + .format); } static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) @@ -1303,23 +1309,21 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) .phy_counters, pport_phy_layer_cntrs_stats_desc, i)); - if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) - for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++) - mlx5e_ethtool_put_stat( - data, - MLX5E_READ_CTR64_BE( - &priv->stats.pport.phy_statistical_counters, - pport_phy_statistical_stats_desc, i)); + for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(mdev); i++) + mlx5e_ethtool_put_stat( + data, + MLX5E_READ_CTR64_BE( + &priv->stats.pport.phy_statistical_counters, + pport_phy_statistical_stats_desc, i)); - if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) - for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++) - mlx5e_ethtool_put_stat( - data, - MLX5E_READ_CTR64_BE( - &priv->stats.pport - .phy_statistical_counters, - pport_phy_statistical_err_lanes_stats_desc, - i)); + for (i = 0; + i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(mdev); + i++) + mlx5e_ethtool_put_stat( + data, + MLX5E_READ_CTR64_BE( + &priv->stats.pport.phy_statistical_counters, + pport_phy_statistical_err_lanes_stats_desc, i)); } static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy)