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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn CC: Gal Pressman , Mark Bloch , "Moshe Shemesh" , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , "Jonathan Corbet" , , , , , Yael Chemla Subject: [PATCH net-next 4/4] net/mlx5e: Expose port reset cycle recovery counter via ethtool Date: Thu, 13 Mar 2025 21:24:46 +0200 Message-ID: <1741893886-188294-5-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1741893886-188294-1-git-send-email-tariqt@nvidia.com> References: <1741893886-188294-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E60:EE_|DS7PR12MB6357:EE_ X-MS-Office365-Filtering-Correlation-Id: 974c9b4b-64bd-42cc-35fe-08dd6264e151 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: osbrk686ddROyn/SXl9D6MKumf5o9FJD82EtCK8WUKB+Ywuai4aVEdZ3EhsaEh67um2tEvfrSg4N1En0JQKixfa3/XeFfTRv+V+dI2gdCab5Ii/r//VOJCWwWTKCt3tHek9aOPLVK7+pXJZOIMxQ4hCTgHko/zSxOpatYwmFEdFD2Al9uff2PKpLyQrxO8BRcL6Hg3wBQH+8A5TU4rzm7wPTyLi6vQBM+aXmVIWaDDAAe10Wy9N5bNo6fxxrBveJ++FfL/coTEJY58kUDrMOSW2gTXRcU47NpHcbZ1OG88La6kSG/3KpLy3kLrd2ahELbzQL1yPTksOHUpLaEfsCLXq8tmkdKR9n4bwwBMq56Dqb9fEcgcyjtAadsxI3fAUXhWDzpVTBO2s7PFy95IYjPvEWXvWK61W+wZrcjnhpeN4z1t46wJwA61j6UoNnDXfttNgeMZmqVY7Pn0P+McSo97GNH5MiaP+NR7rmJxBqODBQEdY0XiNWO+wYPIMvwpb6uCTNuc+6sIHshMcvZWPPYSk4LTAXax39m5Y3IXVk5DHftz7I7OwWrXcnWyW7bi1cWYyRUKLjKYotELI+QVM4uqz8qBRLNEFjrjpwBCZbnpC/JAgE6jIuXt6apnbRtNAOw4JjjEL9aBAhbV37rP4DjlIjAqR0V59CTc5e6oJnaxHWYrq9II54WWbpnOSfgjCdKQNk8MWxwkotNcAKkxYxu8ZTWDLILDqmCCLyn2JdcbbocoUBHBDGI82TDFWJbBimTZFAHgn9lCjlUnYcS4jG5k+U3gZXAaNHx+FUeP+gab17r3To6tPeqQdU00G+ZU4KMT7/Q9xdGX80ie89nM5ndffdCs292Vhksrah10LqH3Sdtw1sI2beKkHEr3BJfN+8QHCer/mBQuAaT3EvDdKnBK01A6fBRR0u9mhoeo6f/TqIM4w4ujvwJwIhTCmDMI9h3a/ZZk1UoV+FEF1etUqCgvIBxoc6J9GJx/zif1V9yWIMTcaVXdCG6HFo1/kO8j6wwqAjLj7ADiYvpHTrYgiZhUBPzWFRp1619ayFDP4cW0dGS+YDc5npzhQtVPsBZQuQwb9M63V142cKItjVqlfCau+1aPrmu0e8nyaMxSESoByINACsbdKWZ5kfkZ+bbtVilhSThrPF4Fh2RjJl+Atv5Cmq1Xp6LEJfVOlxbeBGQiT7tguEKhTwkTT0nw7yOJDGzmbYpRmuwmeuvUKzOF0NBxUrwW5N1pI7M6A4iuDepgGs5t+V26m1+hguJUTyz9QElJn4Lu66qvppkrCIxk2xSQch/kBkY860an79yyPmT3oDL3JvOluBslssCoan3pKq5zgSYrpcgbvnPw2+rLSNCgkf3SGq/J4PzkXrxnfTFvsEBwQBhVkr+bRp4+ldARWMwjl0PtpeF8gxyr6wxHobT9VkucdNxMOj/RGMnymLr/POnXN4RplhHOUAoZBqNyqSDUCiCO94e/ry7KDgXbBhFg== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2025 19:25:57.0894 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 974c9b4b-64bd-42cc-35fe-08dd6264e151 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E60.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6357 X-Patchwork-Delegate: kuba@kernel.org From: Yael Chemla Display recovery event of PPCNT recovery counters group. Counts (per link) the number of total successful recovery events of any recovery types during port reset cycle. Signed-off-by: Yael Chemla Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/counters.rst | 5 +++ .../ethernet/mellanox/mlx5/core/en_stats.c | 44 ++++++++++++++++--- .../ethernet/mellanox/mlx5/core/en_stats.h | 4 ++ 3 files changed, 48 insertions(+), 5 deletions(-) diff --git a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst b/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst index 99d95be4d159..f9a1cf370b5a 100644 --- a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst +++ b/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst @@ -1082,6 +1082,11 @@ like flow control, FEC and more. need to replace the cable/transceiver. - Error + * - `total_success_recovery_phy` + - The number of total successful recovery events of any type during + ports reset cycle. + - Error + * - `rx_out_of_buffer` - Number of times receive queue had no software buffers allocated for the adapter's incoming traffic. diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c index a417962acfa9..acb00fd7efa4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -1250,12 +1250,22 @@ pport_phy_statistical_err_lanes_stats_desc[] = { { "rx_err_lane_3_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane3) }, }; +#define PPORT_PHY_RECOVERY_OFF(c) \ + MLX5_BYTE_OFF(ppcnt_reg, counter_set.phys_layer_recovery_cntrs.c) +static const struct counter_desc +pport_phy_recovery_cntrs_stats_desc[] = { + { "total_success_recovery_phy", + PPORT_PHY_RECOVERY_OFF(total_successful_recovery_events) } +}; + #define NUM_PPORT_PHY_LAYER_COUNTERS \ ARRAY_SIZE(pport_phy_layer_cntrs_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_COUNTERS \ ARRAY_SIZE(pport_phy_statistical_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS \ ARRAY_SIZE(pport_phy_statistical_err_lanes_stats_desc) +#define NUM_PPORT_PHY_RECOVERY_COUNTERS \ + ARRAY_SIZE(pport_phy_recovery_cntrs_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(dev) \ (MLX5_CAP_PCAM_FEATURE(dev, ppcnt_statistical_group) ? \ @@ -1263,6 +1273,9 @@ pport_phy_statistical_err_lanes_stats_desc[] = { #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(dev) \ (MLX5_CAP_PCAM_FEATURE(dev, per_lane_error_counters) ? \ NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0) +#define NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(dev) \ + (MLX5_CAP_PCAM_FEATURE(dev, ppcnt_recovery_counters) ? \ + NUM_PPORT_PHY_RECOVERY_COUNTERS : 0) static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) { @@ -1275,6 +1288,7 @@ static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) num_stats += NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(mdev); + num_stats += NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev); return num_stats; } @@ -1295,6 +1309,10 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy) ethtool_puts(data, pport_phy_statistical_err_lanes_stats_desc[i] .format); + + for (i = 0; i < NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev); i++) + ethtool_puts(data, + pport_phy_recovery_cntrs_stats_desc[i].format); } static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) @@ -1324,6 +1342,13 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) MLX5E_READ_CTR64_BE( &priv->stats.pport.phy_statistical_counters, pport_phy_statistical_err_lanes_stats_desc, i)); + + for (i = 0; i < NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev); i++) + mlx5e_ethtool_put_stat( + data, + MLX5E_READ_CTR32_BE( + &priv->stats.pport.phy_recovery_counters, + pport_phy_recovery_cntrs_stats_desc, i)); } static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy) @@ -1339,12 +1364,21 @@ static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy) MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); - if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) - return; + if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) { + out = pstats->phy_statistical_counters; + MLX5_SET(ppcnt_reg, in, grp, + MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); + mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, + 0); + } - out = pstats->phy_statistical_counters; - MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); - mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); + if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_recovery_counters)) { + out = pstats->phy_recovery_counters; + MLX5_SET(ppcnt_reg, in, grp, + MLX5_PHYSICAL_LAYER_RECOVERY_GROUP); + mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, + 0); + } } void mlx5e_get_link_ext_stats(struct net_device *dev, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h index 5961c569cfe0..0d87947e348d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h @@ -309,6 +309,9 @@ struct mlx5e_vport_stats { #define PPORT_PHY_STATISTICAL_GET(pstats, c) \ MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \ counter_set.phys_layer_statistical_cntrs.c##_high) +#define PPORT_PHY_RECOVERY_GET(pstats, c) \ + MLX5_GET64(ppcnt_reg, (pstats)->phy_recovery_counters, \ + counter_set.phys_layer_recovery_cntrs.c) #define PPORT_PER_PRIO_GET(pstats, prio, c) \ MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \ counter_set.eth_per_prio_grp_data_layout.c##_high) @@ -324,6 +327,7 @@ struct mlx5e_pport_stats { __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; + __be64 phy_recovery_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];