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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Gal Pressman , Leon Romanovsky , "Yael Chemla" , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , "Jonathan Corbet" , , , , , Kalesh Anakkur Purayil , Jacob Keller , Stanislav Fomichev Subject: [PATCH net-next V2 4/4] net/mlx5e: Expose port reset cycle recovery counter via ethtool Date: Sun, 16 Mar 2025 10:14:36 +0200 Message-ID: <1742112876-2890-5-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1742112876-2890-1-git-send-email-tariqt@nvidia.com> References: <1742112876-2890-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004685:EE_|SA3PR12MB7974:EE_ X-MS-Office365-Filtering-Correlation-Id: 7d53355e-b07d-49b3-f47e-08dd6462b10a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: xVmNA51KZfBIPyl99NdsyjN7/M/fNCzQ8iZFtgUXQbGLg17wOy79q3pd9EVCWsNoCuuODx44zibabyAXE1PZ1d2YYywpYRfpvVr6N+KpkU9XouJ1ZR8t/uv6wzxH+NFbnckvoqbSqBq99zP3gJpA5lgkvzZmaxy9J6lTmt38pMzCyfXhRzYeNaq4gitwXfiXyU1aDHNZpO6zFpcXqPqc4NPNKRwnntyrICydCZMKLRO1dItl0pgt9FRjQXMGnM/4XGJhVRxdL85aBWheqtbYO3IGjdxtMe3Gl9Cty6tCpb84mA3J4esMmLHX+jN6H+IpjkFaHBEPQ3zetAaCY4Q9EeA3e86sYH0ScRCxOSoq58ymsD1kB0BEuoPZmSzYdx87KNu5ygJrSd/Tg4qSwukpkareXZRYf3j2/sgFa83JNpiLtpRs0IV/QgCEyCM7Ce02c0X4ZZ9Ujs/QCDiKo8aedrbDAkk1l7AUCXmXMuZfGfVFU0NxBqGAlbZ62F+QWVFHQqHww5qLXMsC7ImPqO78fAHTVoshC1FBDfizQMpPA1sBIS+x2vdkzri2gUPHKuJGVlvunJ6TvROypUwFtM2BlpTobnePjgquU2s4Fjc8IvDrXBDnyM2DYMa0ZWRWw11W+1sJIeoMcPtsskyV+kzELDw/GDPkwpLr1p1VyAV3HLgSNu6ou33vLrjnp3YAcBHh4XYE935yXR1ZkRd+YFRcDjENIjxNMa60imXsri/+t9fDnzhwAl4KlNmlE++Zg0KDeoxiiDqXZGtPdJqM1AmENxDmOqgit56wrHbYLQmRe8znGT7lXRLfyuBlHNj/9q9NeTo03zwGP/Od6yFvr6/GM5MrVgVH6KNr35dPXs4/Brjo6YL7ZNrfhF0KQf/b1DCWfRYNkEz9aH8oFrRwRNCrUUdRxgCzJ/2nU5guPEhYezTzrTyylZ4UDMu3RflMIcd19P7X54B+Ln+3igi8TuIlEkcZlRECP+6CUtRe1/ypOiMylKLirAykkh5fk9khe8h963NVVImIEp0WJgJGnPZBp3bM/PYpJPpdD4oXN/qPvIhQ/oAMRa3XVAi8Tx1mJdpSdKMQk4FlGAaxB9f07wvC/5vu2TVHlLeev6B5sKC+1TCFo6J5QxS/4T7DD5E/+JL+XuayUHUjBUqEEBJwYLiqHJp9CEvOFNnV1M6finzo+I/DDiU75GOaHctarE8xl9mPkNIpeLtBny1CpAd1rDKli1lHaXswmbGaJ/tQdEtrhpUNRGxXo8xXkBdV/BsdwmG32h9ehLQqFDmtdCpSQC7SP98TgIs5NQi9Uc0l5HtYRlXtHLwmVdh4ntKwCMIn3teB21/IUj4K8kN7OHuxHRo651z7ky6RYuF79VsK8CGQA364AvsCtiXozp4z5jaij0CUbcsGQNpNmKGsogdmbp1n8tXg6vv3cCYUFABefGVS7tSUtkxkv+hKenYf7cnCUrqNiVTJLnJ5XisarZl5ZN8uyNUdogY5DNEXkclwhanthVY= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2025 08:15:19.4304 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7d53355e-b07d-49b3-f47e-08dd6462b10a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004685.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7974 X-Patchwork-Delegate: kuba@kernel.org From: Yael Chemla Display recovery event of PPCNT recovery counters group. Counts (per link) the number of total successful recovery events of any recovery types during port reset cycle. Signed-off-by: Yael Chemla Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Jacob Keller --- .../ethernet/mellanox/mlx5/counters.rst | 5 +++ .../ethernet/mellanox/mlx5/core/en_stats.c | 44 ++++++++++++++++--- .../ethernet/mellanox/mlx5/core/en_stats.h | 4 ++ 3 files changed, 48 insertions(+), 5 deletions(-) diff --git a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst b/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst index 99d95be4d159..43d72c8b713b 100644 --- a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst +++ b/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst @@ -1082,6 +1082,11 @@ like flow control, FEC and more. need to replace the cable/transceiver. - Error + * - `total_success_recovery_phy` + - The number of total successful recovery events of any type during + ports reset cycle. + - Error + * - `rx_out_of_buffer` - Number of times receive queue had no software buffers allocated for the adapter's incoming traffic. diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c index a417962acfa9..acb00fd7efa4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -1250,12 +1250,22 @@ pport_phy_statistical_err_lanes_stats_desc[] = { { "rx_err_lane_3_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane3) }, }; +#define PPORT_PHY_RECOVERY_OFF(c) \ + MLX5_BYTE_OFF(ppcnt_reg, counter_set.phys_layer_recovery_cntrs.c) +static const struct counter_desc +pport_phy_recovery_cntrs_stats_desc[] = { + { "total_success_recovery_phy", + PPORT_PHY_RECOVERY_OFF(total_successful_recovery_events) } +}; + #define NUM_PPORT_PHY_LAYER_COUNTERS \ ARRAY_SIZE(pport_phy_layer_cntrs_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_COUNTERS \ ARRAY_SIZE(pport_phy_statistical_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS \ ARRAY_SIZE(pport_phy_statistical_err_lanes_stats_desc) +#define NUM_PPORT_PHY_RECOVERY_COUNTERS \ + ARRAY_SIZE(pport_phy_recovery_cntrs_stats_desc) #define NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(dev) \ (MLX5_CAP_PCAM_FEATURE(dev, ppcnt_statistical_group) ? \ @@ -1263,6 +1273,9 @@ pport_phy_statistical_err_lanes_stats_desc[] = { #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(dev) \ (MLX5_CAP_PCAM_FEATURE(dev, per_lane_error_counters) ? \ NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0) +#define NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(dev) \ + (MLX5_CAP_PCAM_FEATURE(dev, ppcnt_recovery_counters) ? \ + NUM_PPORT_PHY_RECOVERY_COUNTERS : 0) static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) { @@ -1275,6 +1288,7 @@ static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy) num_stats += NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(mdev); + num_stats += NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev); return num_stats; } @@ -1295,6 +1309,10 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy) ethtool_puts(data, pport_phy_statistical_err_lanes_stats_desc[i] .format); + + for (i = 0; i < NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev); i++) + ethtool_puts(data, + pport_phy_recovery_cntrs_stats_desc[i].format); } static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) @@ -1324,6 +1342,13 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy) MLX5E_READ_CTR64_BE( &priv->stats.pport.phy_statistical_counters, pport_phy_statistical_err_lanes_stats_desc, i)); + + for (i = 0; i < NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev); i++) + mlx5e_ethtool_put_stat( + data, + MLX5E_READ_CTR32_BE( + &priv->stats.pport.phy_recovery_counters, + pport_phy_recovery_cntrs_stats_desc, i)); } static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy) @@ -1339,12 +1364,21 @@ static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy) MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); - if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) - return; + if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) { + out = pstats->phy_statistical_counters; + MLX5_SET(ppcnt_reg, in, grp, + MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); + mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, + 0); + } - out = pstats->phy_statistical_counters; - MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); - mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); + if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_recovery_counters)) { + out = pstats->phy_recovery_counters; + MLX5_SET(ppcnt_reg, in, grp, + MLX5_PHYSICAL_LAYER_RECOVERY_GROUP); + mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, + 0); + } } void mlx5e_get_link_ext_stats(struct net_device *dev, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h index 5961c569cfe0..0d87947e348d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h @@ -309,6 +309,9 @@ struct mlx5e_vport_stats { #define PPORT_PHY_STATISTICAL_GET(pstats, c) \ MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \ counter_set.phys_layer_statistical_cntrs.c##_high) +#define PPORT_PHY_RECOVERY_GET(pstats, c) \ + MLX5_GET64(ppcnt_reg, (pstats)->phy_recovery_counters, \ + counter_set.phys_layer_recovery_cntrs.c) #define PPORT_PER_PRIO_GET(pstats, prio, c) \ MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \ counter_set.eth_per_prio_grp_data_layout.c##_high) @@ -324,6 +327,7 @@ struct mlx5e_pport_stats { __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; + __be64 phy_recovery_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)]; __be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];