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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Gal Pressman , Leon Romanovsky , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , , , , Moshe Shemesh , Mark Bloch Subject: [PATCH net-next 1/5] net/mlx5: Lag, use port selection tables when available Date: Wed, 19 Mar 2025 16:02:59 +0200 Message-ID: <1742392983-153050-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1742392983-153050-1-git-send-email-tariqt@nvidia.com> References: <1742392983-153050-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|PH7PR12MB8039:EE_ X-MS-Office365-Filtering-Correlation-Id: be7c1365-8ffc-48fb-8e6d-08dd66eef603 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: Gk1jms/bRV71z0nVdrdx94pvd9LTjHAFu50lJki3G9OLF8X+mYTZuEceS1YlWCFw/ucXyvetIJk5hDfIoTUhZtSh3tf80TyrpTyaUyQbhSWQT5rmTpasIsLEM2BgqSRo4JyPO/7kn5HmSimRgHVwdOBoW2nJww2EjoNVEWGu2t2TZNdlFpNX7Hv3xfhjnnmdfp96UWEHps1xS7xuBys3I/1tzUv3VmP3vnHntsdyyDNR+90ergClbwrhu7RqarFPYBOyEmoECfksQ/loTLiQgLL5XB/g22346nhz78Gpx+FXR32nbzd6U/hM+DbrFQtFPFYCezH0P4Iz1hOBcdM+86OsghNBC9u64dc2J/IxCFrAd5CUmWZwDoP0v1EnG8Tc+q0al8WVuGtl4LbC9Yusmw9g0M9lfXk9ocRWMqjbW2Rlxi3XVE7dvdv5Xuq8PtgH2bDvEus9Wp4pHnkZI3hMLn1UMTJBrt1JY/GUDBKmEdpJ+52CEvt8TK1jvRNkCRDyiSW5ZEUL4xXOa9EjPGMAKtlI9NzhDliXB5aCSoFoCW1J06o24mbmP2oGOomy7iK4GRjRlIShavvZdhUbTmcRXHweI03y97PjgXfMLw1dCfDzRo1J9XCZgqItMOiw4W+gPdXRB0+64WJfuzf81XLOcSwYPfTC4IiSgz9bGusY7+VN/yyq/v5ho1ZqYPecZL51siLXL2B3BFzZ0XaFxGHAjvYTt9OLLfJa0T8xExBMlwsWTmjKFVahIzkC2RbmJ95gaHFUbxSNU1Lt2fOr47WO7pfqECeovEbdkDFxZ3ChLQ7muv8FgnSdpMQgTAeiiXGivCPw/w8bXI9ayNgWsuLWylo92S083fMDT5p0Oo1gBvEjVj5GtXybYaxUOwdbLnQC5VKMWwn31MwI9oOqeHvd6sPeGpLYVyZji/L9q7aWNZ8ESZD/IxzZ4kKEIb2logEErP87GkIQ+fnLMddFm0YDnHSwg0C7iptD0bFr1X6j1D9RVMYkMnLLBpA2NtWha3eaikHgDIVXZUc2Xo5ywBkDUpGqvw9wgyv+0/kJ7/3TQP2+sLB0lHbuQdwoLNDR6Cif1FFPsq7mcelH9XP794EP/cK8TujN1pQkmSZWd/2wFoF/BpYcnmX8XL6BPB0RF9suU0f0VYPNntBp58tzK5DdoLlcnOX/Vc0R1RZCPW0manfiIwM0vH0j4+XssVPKTTxu7t/6X62U/U4ZnUvK4MnhlrK+hebbWE+nBaCnJ1BOManCjQ0a7hBf6qV8bJN2kJqWI7aopqFT2M11dPR2sZpuyYQ2Rry0Zu1i3XQiVo8HDrJAOPiDM8HJs/sk/kIDJwpnHkLLsabgMFumRzLOJUHNnZu42xffKAluH1Sg8RPbP81abyLS5wEJvAJFBqe3B03cs/c8ObfzYQ27gacIHXknwzSasoapGlMourfsCIjpo54GyXi7IjznUNx5axO5san7i8T+YJMGCv5xfatTr6PUpw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2025 14:04:27.1375 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be7c1365-8ffc-48fb-8e6d-08dd66eef603 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8039 X-Patchwork-Delegate: kuba@kernel.org From: Mark Bloch As queue affinity is being deprecated and will no longer be supported in the future, Always check for the presence of the port selection namespace. When available, leverage it to distribute traffic across the physical ports via steering, ensuring compatibility with future NICs. Signed-off-by: Mark Bloch Reviewed-by: Maor Gottlieb Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 38 +++++-------------- 1 file changed, 9 insertions(+), 29 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c index ed2ba272946b..e856edf6bbb5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -584,8 +584,9 @@ void mlx5_modify_lag(struct mlx5_lag *ldev, } } -static int mlx5_lag_set_port_sel_mode_roce(struct mlx5_lag *ldev, - unsigned long *flags) +static int mlx5_lag_set_port_sel_mode(struct mlx5_lag *ldev, + enum mlx5_lag_mode mode, + unsigned long *flags) { int first_idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); struct mlx5_core_dev *dev0; @@ -593,7 +594,12 @@ static int mlx5_lag_set_port_sel_mode_roce(struct mlx5_lag *ldev, if (first_idx < 0) return -EINVAL; + if (mode == MLX5_LAG_MODE_MPESW || + mode == MLX5_LAG_MODE_MULTIPATH) + return 0; + dev0 = ldev->pf[first_idx].dev; + if (!MLX5_CAP_PORT_SELECTION(dev0, port_select_flow_table)) { if (ldev->ports > 2) return -EINVAL; @@ -608,32 +614,10 @@ static int mlx5_lag_set_port_sel_mode_roce(struct mlx5_lag *ldev, return 0; } -static void mlx5_lag_set_port_sel_mode_offloads(struct mlx5_lag *ldev, - struct lag_tracker *tracker, - enum mlx5_lag_mode mode, - unsigned long *flags) -{ - int first_idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); - struct lag_func *dev0; - - if (first_idx < 0 || mode == MLX5_LAG_MODE_MPESW) - return; - - dev0 = &ldev->pf[first_idx]; - if (MLX5_CAP_PORT_SELECTION(dev0->dev, port_select_flow_table) && - tracker->tx_type == NETDEV_LAG_TX_TYPE_HASH) { - if (ldev->ports > 2) - ldev->buckets = MLX5_LAG_MAX_HASH_BUCKETS; - set_bit(MLX5_LAG_MODE_FLAG_HASH_BASED, flags); - } -} - static int mlx5_lag_set_flags(struct mlx5_lag *ldev, enum mlx5_lag_mode mode, struct lag_tracker *tracker, bool shared_fdb, unsigned long *flags) { - bool roce_lag = mode == MLX5_LAG_MODE_ROCE; - *flags = 0; if (shared_fdb) { set_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, flags); @@ -643,11 +627,7 @@ static int mlx5_lag_set_flags(struct mlx5_lag *ldev, enum mlx5_lag_mode mode, if (mode == MLX5_LAG_MODE_MPESW) set_bit(MLX5_LAG_MODE_FLAG_FDB_SEL_MODE_NATIVE, flags); - if (roce_lag) - return mlx5_lag_set_port_sel_mode_roce(ldev, flags); - - mlx5_lag_set_port_sel_mode_offloads(ldev, tracker, mode, flags); - return 0; + return mlx5_lag_set_port_sel_mode(ldev, mode, flags); } char *mlx5_get_str_port_sel_mode(enum mlx5_lag_mode mode, unsigned long flags)