| Message ID | 20201202141502.21265-1-elder@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [v2,net-next] net: ipa: fix build-time bug in ipa_hardware_config_qsb() | expand |
| Context | Check | Description |
|---|---|---|
| netdev/cover_letter | success | Link |
| netdev/fixes_present | success | Link |
| netdev/patch_count | success | Link |
| netdev/tree_selection | success | Clearly marked for net-next |
| netdev/subject_prefix | success | Link |
| netdev/source_inline | success | Was 0 now: 0 |
| netdev/verify_signedoff | success | Link |
| netdev/module_param | success | Was 0 now: 0 |
| netdev/build_32bit | success | Errors and warnings before: 0 this patch: 0 |
| netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| netdev/verify_fixes | success | Link |
| netdev/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 8 lines checked |
| netdev/build_allmodconfig_warn | success | Errors and warnings before: 0 this patch: 0 |
| netdev/header_inline | success | Link |
| netdev/stable | success | Stable not CCed |
On Wed, 2 Dec 2020 08:15:02 -0600 Alex Elder wrote: > Jon Hunter reported observing a build bug in the IPA driver: > https://lore.kernel.org/netdev/5b5d9d40-94d5-5dad-b861-fd9bef8260e2@nvidia.com > > The problem is that the QMB0 max read value set for IPA v4.5 (16) is > too large to fit in the 4-bit field. > > The actual value we want is 0, which requests that the hardware use > the maximum it is capable of. > > Reported-by: Jon Hunter <jonathanh@nvidia.com> > Tested-by: Jon Hunter <jonathanh@nvidia.com> > Signed-off-by: Alex Elder <elder@linaro.org> Applied, thanks!
diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index d0768452c15cf..84bb8ae927252 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -288,7 +288,7 @@ static void ipa_hardware_config_qsb(struct ipa *ipa) max1 = 0; /* PCIe not present */ break; case IPA_VERSION_4_5: - max0 = 16; + max0 = 0; /* No limit (hardware maximum) */ break; } val = u32_encode_bits(max0, GEN_QMB_0_MAX_READS_FMASK);