From patchwork Thu Dec 3 10:30:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steen Hegelund X-Patchwork-Id: 11948393 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C95FC71156 for ; Thu, 3 Dec 2020 10:32:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 336B720C56 for ; Thu, 3 Dec 2020 10:32:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388926AbgLCKcQ (ORCPT ); Thu, 3 Dec 2020 05:32:16 -0500 Received: from esa1.microchip.iphmx.com ([68.232.147.91]:9744 "EHLO esa1.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387620AbgLCKcQ (ORCPT ); Thu, 3 Dec 2020 05:32:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1606991535; x=1638527535; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HYvqfDOJAQzsbDFrol1vkz2s/fsDFmkTjeSVK52uWyE=; b=gYQB+TRi0ltbNTLaqiEthV7jWmqT+zdcGBH2WE4zjL4sl5VSgDNJxeCb tcS8mQkveQqNVR9O/HpiDJpgF4DOwjdZmzDn9YVKIkmip0YRmHHJgVHlw akV+d3f6bgeOvOu4oiEqT36SrwUlaU7RtfKWgmgQgJ7goomUQuglC9vWN gL622iguclTNWCs1pn7jGJh6GCXc2vRk6tn9+AfE1nkvsoGrI1Sb8pzvv uVChzzDZyTSXWW+XFlDF0u8AdddLpI85iG78++e67JsD9F5Q6JmzjnlhI mw4LtUhuAmlS4iAsNnpC6DOeUF7rkB+oB8jxhXTegvpg6FSkRhI9YW1MY w==; IronPort-SDR: /muQGuZvVJ63hGcW/XN7V9Ns/4opOGqoyFWx44j8GQ5bjpDGYv0GBXIXbTA9MDga9gxnkEGKS7 Pf0nu2KZnigbVYugdNaWCOZp2Q+Gnyz96F/Oo3ZrHMl7N/Q2/KlcBFt2AD4KViCQaR8s9Vkoea J0oER7TpzDjfFjnusVjGc+SZAK9NBsyQc9codokD8HwcFqqIQYPvxpZ01PD+t+//siCJ3FaBBU qe3QeM3ITclO5K9dbVXU8CkOfSZ6XDJ3XWamD4uYl1ovbJTA3SOkNRY8Hf59ZWdmKRu1oLcZhz 7F4= X-IronPort-AV: E=Sophos;i="5.78,389,1599548400"; d="scan'208";a="105989344" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Dec 2020 03:30:41 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 3 Dec 2020 03:30:41 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 3 Dec 2020 03:30:39 -0700 From: Steen Hegelund To: Kishon Vijay Abraham I , Vinod Koul CC: Steen Hegelund , Alexandre Belloni , Lars Povlsen , Bjarni Jonasson , Microchip UNG Driver List , , Subject: [PATCH v8 4/4] arm64: dts: sparx5: Add Sparx5 serdes driver node Date: Thu, 3 Dec 2020 11:30:15 +0100 Message-ID: <20201203103015.3735373-5-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201203103015.3735373-1-steen.hegelund@microchip.com> References: <20201203103015.3735373-1-steen.hegelund@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add Sparx5 serdes driver node, and enable it generally for all reference boards. Signed-off-by: Lars Povlsen Signed-off-by: Steen Hegelund --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 8e7724d413fb..797601a9d542 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -287,5 +287,13 @@ tmon0: tmon@610508110 { #thermal-sensor-cells = <0>; clocks = <&ahb_clk>; }; + + serdes: serdes@10808000 { + compatible = "microchip,sparx5-serdes"; + #phy-cells = <1>; + clocks = <&sys_clk>; + reg = <0x6 0x10808000 0x5d0000>; + }; + }; };