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Mon, 7 Dec 2020 10:51:41 +0000 From: Joakim Zhang To: peppe.cavallaro@st.com, alexandre.torgue@st.com, joabreu@synopsys.com, davem@davemloft.net, kuba@kernel.org Cc: netdev@vger.kernel.org, linux-imx@nxp.com Subject: [PATCH V3 5/5] net: stmmac: overwrite the dma_cap.addr64 according to HW design Date: Mon, 7 Dec 2020 18:51:41 +0800 Message-Id: <20201207105141.12550-6-qiangqing.zhang@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201207105141.12550-1-qiangqing.zhang@nxp.com> References: <20201207105141.12550-1-qiangqing.zhang@nxp.com> X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SG2PR0601CA0018.apcprd06.prod.outlook.com (2603:1096:3::28) To DB8PR04MB6795.eurprd04.prod.outlook.com (2603:10a6:10:fa::15) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.71) by SG2PR0601CA0018.apcprd06.prod.outlook.com (2603:1096:3::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.17 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: nu9aA+CEdEict4Sycz2tSooaxfz6WlIH0/f6H/RCfRlV8iLuhr/jAlTOZ018FRH3vcPzqp6/kObVS1mFsf+gb46z8nCPTgrBr3Ic5CmNcB3eOjm6dmkeYmToDOffliBaYLvMAnVI/ovEllXa3PNRBFA75gY6qhPhhRDYkT/UhKlKYKCGferMJ5KZjUXS8aWH3UendjJiZH7RAIA1zW8Hh+q8Z2mz4HEcgkJ4AkoM3Syx9TlTWHITf9F3lGm4iF4f1s2+5qg9fNMq1JcieVZvuPp1QiD0n22l9y9Jt3B99rqJEicGQ/FEEw5fU6Pb5jvdLAUOcFpBTYGBebR3sAxq+19qo1uUCZ2o3mdHSZaUKTvWHg6zlXDwjLhlMNcyLdvl/oOaQ7m1jXFimKZWl4qcBlU4Ca/BHszWz6NH7PBmObZjgcGO+bsEAyOz46OauaDE/o35oL2g8uB1TShSdLUICMZgsXvgPFtWdJoLWjYdfKk00z1gwdJxttkPMz6a6+bPs0r7Z38jd1dD7+3nj2ompZ/SkWKaxXGsEsBKHaP2bOocAM7Ou7wMJYdsB06WISFsNebZKyd1DBadPMwsncUMNMSn+mR5Xm6widywTyyYb7D+VacbtMY7VrYn1L5nsHaexHarSaopyTjg/inlwM6QsZbPYoGowoAJ/xJVX/wZPlKIBSNupmJR5BkiZ70qvOtudGfmRwGjYR3TzOVrPzK0PRJTTSXM918EU8QuAnKwfW0AQfZR91EXfakJyDkowCM89uynyFnFGtXbh7GvBsqOgF7R3EBvetes2wUTdVf3URhErzsNx3ahNRrX0FDFyOAW6fYoVp+sFAcHNSeQ7v2pTIFapgb4brGEk4BedHhHHzAGv3HG2WL9muj+BigZL4MCdxfcOCMKt5/AcQiFI6nHYWLzGlGlo4HxVtqwOqk35V7T0UgCOKr8Tc+j0Ojo6xj3s6hlzWv5C/c+WslTNX1APxAbiwLpu9ZJukORIffO3Pe1/lI+DesM0nfQmRYNVi7B X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 92aadb24-1f1a-4071-2474-08d89a9e14c8 X-MS-Exchange-CrossTenant-AuthSource: DB8PR04MB6795.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2020 10:51:41.8968 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: MjrBmoXf47/4sCAWx0OoddmoHlRAKIqHevSv41W127V1Aryvim3RFjfjOVdycHGofc8uWhglcdUClcM8gQDz2A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0401MB2328 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Fugang Duan The current IP register MAC_HW_Feature1[ADDR64] only defines 32/40/64 bit width, but some SOCs support others like i.MX8MP support 34 bits but it maps to 40 bits width in MAC_HW_Feature1[ADDR64]. So overwrite dma_cap.addr64 according to HW real design. Fixes: 94abdad6974a ("net: ethernet: dwmac: add ethernet glue logic for NXP imx8 chip") Signed-off-by: Fugang Duan Signed-off-by: Joakim Zhang --- drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c | 9 +-------- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 8 ++++++++ include/linux/stmmac.h | 1 + 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c index efef5476a577..223f69da7e95 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c @@ -246,13 +246,7 @@ static int imx_dwmac_probe(struct platform_device *pdev) goto err_parse_dt; } - ret = dma_set_mask_and_coherent(&pdev->dev, - DMA_BIT_MASK(dwmac->ops->addr_width)); - if (ret) { - dev_err(&pdev->dev, "DMA mask set failed\n"); - goto err_dma_mask; - } - + plat_dat->addr64 = dwmac->ops->addr_width; plat_dat->init = imx_dwmac_init; plat_dat->exit = imx_dwmac_exit; plat_dat->fix_mac_speed = imx_dwmac_fix_speed; @@ -272,7 +266,6 @@ static int imx_dwmac_probe(struct platform_device *pdev) err_dwmac_init: err_drv_probe: imx_dwmac_exit(pdev, plat_dat->bsp_priv); -err_dma_mask: err_parse_dt: err_match_data: stmmac_remove_config_dt(pdev, plat_dat); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index d2521ebb8217..c33db79cdd0a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -4945,6 +4945,14 @@ int stmmac_dvr_probe(struct device *device, dev_info(priv->device, "SPH feature enabled\n"); } + /* The current IP register MAC_HW_Feature1[ADDR64] only define + * 32/40/64 bit width, but some SOC support others like i.MX8MP + * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. + * So overwrite dma_cap.addr64 according to HW real design. + */ + if (priv->plat->addr64) + priv->dma_cap.addr64 = priv->plat->addr64; + if (priv->dma_cap.addr64) { ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(priv->dma_cap.addr64)); diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 628e28903b8b..15ca6b4167cc 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -170,6 +170,7 @@ struct plat_stmmacenet_data { int unicast_filter_entries; int tx_fifo_size; int rx_fifo_size; + u32 addr64; u32 rx_queues_to_use; u32 tx_queues_to_use; u8 rx_sched_algorithm;