diff mbox series

[net-next,11/16] net/mlx5: DR, Add STE setters and getters per-device API

Message ID 20210105230333.239456-12-saeed@kernel.org (mailing list archive)
State Accepted
Delegated to: Netdev Maintainers
Headers show
Series [net-next,01/16] net/mlx5: DR, Add infrastructure for supporting several steering formats | expand

Checks

Context Check Description
netdev/apply success Patch already applied to net-next
netdev/tree_selection success Clearly marked for net-next

Commit Message

Saeed Mahameed Jan. 5, 2021, 11:03 p.m. UTC 
From: Yevgeny Kliteynik <kliteyn@nvidia.com>

Extend the STE context struct with various per-device
setters and getters.

Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 .../ethernet/mellanox/mlx5/core/steering/dr_ste.h    | 12 ++++++++++++
 1 file changed, 12 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h
index 0773dad59f93..53bb42978e84 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h
@@ -76,6 +76,7 @@  u16 mlx5dr_ste_conv_bit_to_byte_mask(u8 *bit_mask);
 				 struct mlx5dr_match_param *mask))
 
 struct mlx5dr_ste_ctx {
+	/* Builders */
 	void DR_STE_CTX_BUILDER(eth_l2_src_dst);
 	void DR_STE_CTX_BUILDER(eth_l3_ipv6_src);
 	void DR_STE_CTX_BUILDER(eth_l3_ipv6_dst);
@@ -96,6 +97,17 @@  struct mlx5dr_ste_ctx {
 	void DR_STE_CTX_BUILDER(register_0);
 	void DR_STE_CTX_BUILDER(register_1);
 	void DR_STE_CTX_BUILDER(src_gvmi_qpn);
+
+	/* Getters and Setters */
+	void (*ste_init)(u8 *hw_ste_p, u16 lu_type,
+			 u8 entry_type, u16 gvmi);
+	void (*set_next_lu_type)(u8 *hw_ste_p, u16 lu_type);
+	u16  (*get_next_lu_type)(u8 *hw_ste_p);
+	void (*set_miss_addr)(u8 *hw_ste_p, u64 miss_addr);
+	u64  (*get_miss_addr)(u8 *hw_ste_p);
+	void (*set_hit_addr)(u8 *hw_ste_p, u64 icm_addr, u32 ht_size);
+	void (*set_byte_mask)(u8 *hw_ste_p, u16 byte_mask);
+	u16  (*get_byte_mask)(u8 *hw_ste_p);
 };
 
 extern struct mlx5dr_ste_ctx ste_ctx_v0;