| Message ID | 20210111130657.10703-2-bjarni.jonasson@microchip.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add 100 base-x mode | expand |
| Context | Check | Description |
|---|---|---|
| netdev/cover_letter | success | Link |
| netdev/fixes_present | success | Link |
| netdev/patch_count | success | Link |
| netdev/tree_selection | success | Guessed tree name to be net-next |
| netdev/subject_prefix | success | Link |
| netdev/cc_maintainers | success | CCed 4 of 4 maintainers |
| netdev/source_inline | success | Was 0 now: 0 |
| netdev/verify_signedoff | success | Link |
| netdev/module_param | success | Was 0 now: 0 |
| netdev/build_32bit | success | Errors and warnings before: 624 this patch: 624 |
| netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| netdev/verify_fixes | success | Link |
| netdev/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 22 lines checked |
| netdev/build_allmodconfig_warn | success | Errors and warnings before: 540 this patch: 540 |
| netdev/header_inline | success | Link |
| netdev/stable | success | Stable not CCed |
On Mon, Jan 11, 2021 at 02:06:56PM +0100, Bjarni Jonasson wrote: > Sparx-5 supports this mode and it is missing in the PHY core. > > Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Looks good, thanks. Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> > --- > include/linux/phy.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/include/linux/phy.h b/include/linux/phy.h > index 56563e5e0dc7..dce867222d58 100644 > --- a/include/linux/phy.h > +++ b/include/linux/phy.h > @@ -111,6 +111,7 @@ extern const int phy_10gbit_features_array[1]; > * @PHY_INTERFACE_MODE_10GBASER: 10G BaseR > * @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII > * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN > + * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX > * @PHY_INTERFACE_MODE_MAX: Book keeping > * > * Describes the interface between the MAC and PHY. > @@ -144,6 +145,7 @@ typedef enum { > PHY_INTERFACE_MODE_USXGMII, > /* 10GBASE-KR - with Clause 73 AN */ > PHY_INTERFACE_MODE_10GKR, > + PHY_INTERFACE_MODE_100BASEX, > PHY_INTERFACE_MODE_MAX, > } phy_interface_t; > > @@ -217,6 +219,8 @@ static inline const char *phy_modes(phy_interface_t interface) > return "usxgmii"; > case PHY_INTERFACE_MODE_10GKR: > return "10gbase-kr"; > + case PHY_INTERFACE_MODE_100BASEX: > + return "100base-x"; > default: > return "unknown"; > } > -- > 2.17.1 > >
On Mon, Jan 11, 2021 at 02:06:56PM +0100, Bjarni Jonasson wrote: > Sparx-5 supports this mode and it is missing in the PHY core. > > Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
On Mon, Jan 11, 2021 at 02:06:56PM +0100, Bjarni Jonasson wrote: > Sparx-5 supports this mode and it is missing in the PHY core. > > Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Oh, I forgot - please can we have the new PHY mode documented in Documentation/networking/phy.rst under the "PHY interface modes" section. Thanks.
pon., 11 sty 2021 o 14:54 Bjarni Jonasson <bjarni.jonasson@microchip.com> napisał(a): > Sparx-5 supports this mode and it is missing in the PHY core. > > Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> > --- > include/linux/phy.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/include/linux/phy.h b/include/linux/phy.h > index 56563e5e0dc7..dce867222d58 100644 > --- a/include/linux/phy.h > +++ b/include/linux/phy.h > @@ -111,6 +111,7 @@ extern const int phy_10gbit_features_array[1]; > * @PHY_INTERFACE_MODE_10GBASER: 10G BaseR > * @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII > * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN > + * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX > * @PHY_INTERFACE_MODE_MAX: Book keeping [...] This is kernel-internal interface, so maybe the new mode can be inserted before 1000baseX for easier lookup? Best Regards Michał Mirosław
On Mon, 2021-01-11 at 16:47 +0000, Russell King - ARM Linux admin wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > On Mon, Jan 11, 2021 at 02:06:56PM +0100, Bjarni Jonasson wrote: > > Sparx-5 supports this mode and it is missing in the PHY core. > > > > Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> > > Oh, I forgot - please can we have the new PHY mode documented in > Documentation/networking/phy.rst under the "PHY interface modes" > section. Thanks. > -- > RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ > FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last! Will do that. -- Bjarni Jonasson
On Mon, 2021-01-11 at 20:37 +0100, Michał Mirosław wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > pon., 11 sty 2021 o 14:54 Bjarni Jonasson > <bjarni.jonasson@microchip.com> napisał(a): > > Sparx-5 supports this mode and it is missing in the PHY core. > > > > Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> > > --- > > include/linux/phy.h | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/include/linux/phy.h b/include/linux/phy.h > > index 56563e5e0dc7..dce867222d58 100644 > > --- a/include/linux/phy.h > > +++ b/include/linux/phy.h > > @@ -111,6 +111,7 @@ extern const int phy_10gbit_features_array[1]; > > * @PHY_INTERFACE_MODE_10GBASER: 10G BaseR > > * @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII > > * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN > > + * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX > > * @PHY_INTERFACE_MODE_MAX: Book keeping > > [...] > > This is kernel-internal interface, so maybe the new mode can be > inserted before 1000baseX for easier lookup? > > Best Regards > Michał Mirosław Yes, will do that. -- Bjarni Jonasson Microchip
diff --git a/include/linux/phy.h b/include/linux/phy.h index 56563e5e0dc7..dce867222d58 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -111,6 +111,7 @@ extern const int phy_10gbit_features_array[1]; * @PHY_INTERFACE_MODE_10GBASER: 10G BaseR * @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN + * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX * @PHY_INTERFACE_MODE_MAX: Book keeping * * Describes the interface between the MAC and PHY. @@ -144,6 +145,7 @@ typedef enum { PHY_INTERFACE_MODE_USXGMII, /* 10GBASE-KR - with Clause 73 AN */ PHY_INTERFACE_MODE_10GKR, + PHY_INTERFACE_MODE_100BASEX, PHY_INTERFACE_MODE_MAX, } phy_interface_t; @@ -217,6 +219,8 @@ static inline const char *phy_modes(phy_interface_t interface) return "usxgmii"; case PHY_INTERFACE_MODE_10GKR: return "10gbase-kr"; + case PHY_INTERFACE_MODE_100BASEX: + return "100base-x"; default: return "unknown"; }
Sparx-5 supports this mode and it is missing in the PHY core. Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> --- include/linux/phy.h | 4 ++++ 1 file changed, 4 insertions(+)