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[193.12.47.89]) by smtp.gmail.com with ESMTPSA id 198sm1085686lfn.51.2021.01.15.17.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 17:25:53 -0800 (PST) From: Tobias Waldekranz To: davem@davemloft.net, kuba@kernel.org Cc: andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, roopa@nvidia.com, nikolay@nvidia.com, netdev@vger.kernel.org Subject: [RFC net-next 7/7] net: dsa: mv88e6xxx: Request assisted learning on CPU port Date: Sat, 16 Jan 2021 02:25:15 +0100 Message-Id: <20210116012515.3152-8-tobias@waldekranz.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210116012515.3152-1-tobias@waldekranz.com> References: <20210116012515.3152-1-tobias@waldekranz.com> Organization: Westermo Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC While the hardware is capable of performing learning on the CPU port, it requires alot of additions to the bridge's forwarding path in order to handle multi-destination traffic correctly. Until that is in place, opt for the next best thing and let DSA sync the relevant addresses down to the hardware FDB. Signed-off-by: Tobias Waldekranz --- drivers/net/dsa/mv88e6xxx/chip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 91286d7b12c7..398f3cc8d2f3 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -5726,6 +5726,7 @@ static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) ds->ops = &mv88e6xxx_switch_ops; ds->ageing_time_min = chip->info->age_time_coeff; ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; + ds->assisted_learning_on_cpu_port = true; /* Some chips support up to 32, but that requires enabling the * 5-bit port mode, which we do not support. 640k^W16 ought to