From patchwork Mon Mar 29 13:40:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ong Boon Leong X-Patchwork-Id: 12170147 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98FC8C433C1 for ; Mon, 29 Mar 2021 13:37:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 591AF61932 for ; Mon, 29 Mar 2021 13:37:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231510AbhC2Ng4 (ORCPT ); Mon, 29 Mar 2021 09:36:56 -0400 Received: from mga03.intel.com ([134.134.136.65]:45673 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231571AbhC2Ng1 (ORCPT ); Mon, 29 Mar 2021 09:36:27 -0400 IronPort-SDR: 9u1ZPvYnGTYfOj67oW/8BHx6bFs0SUZqqFlqQtcri3Twpu8s4WYhkI9jzNbGD9uI3XjGegIvIq Of4VFa3H37hA== X-IronPort-AV: E=McAfee;i="6000,8403,9938"; a="191578695" X-IronPort-AV: E=Sophos;i="5.81,287,1610438400"; d="scan'208";a="191578695" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2021 06:36:27 -0700 IronPort-SDR: +l9e/G6tHjwa1KuU/ooNwJpc6WXAW1rN2dalrWNZudQesddftnUyZxNu4rbH9wawqVDBTu4sbQ ugaEgoWhgP0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,287,1610438400"; d="scan'208";a="411079330" Received: from glass.png.intel.com ([10.158.65.59]) by fmsmga008.fm.intel.com with ESMTP; 29 Mar 2021 06:36:22 -0700 From: Ong Boon Leong To: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S . Miller" , Jakub Kicinski , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend Cc: Maxime Coquelin , Andrii Nakryiko , Martin KaFai Lau , Song Liu , Yonghong Song , KP Singh , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, Ong Boon Leong Subject: [PATCH net-next 1/6] stmmac: intel: set IRQ affinity hint for multi MSI vectors Date: Mon, 29 Mar 2021 21:40:08 +0800 Message-Id: <20210329134013.9516-2-boon.leong.ong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210329134013.9516-1-boon.leong.ong@intel.com> References: <20210329134013.9516-1-boon.leong.ong@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Intel mGBE has independent hardware IRQ resources for TX and RX DMA operation. In preparation to support XDP TX, we add IRQ affinity hint to group both RX and TX queue of the same queue ID to the same CPU. Signed-off-by: Ong Boon Leong --- drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index 08b4852eed4c..53a24932a192 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -810,6 +810,7 @@ static int stmmac_config_multi_msi(struct pci_dev *pdev, struct plat_stmmacenet_data *plat, struct stmmac_resources *res) { + cpumask_t cpu_mask; int ret; int i; @@ -832,12 +833,18 @@ static int stmmac_config_multi_msi(struct pci_dev *pdev, for (i = 0; i < plat->rx_queues_to_use; i++) { res->rx_irq[i] = pci_irq_vector(pdev, plat->msi_rx_base_vec + i * 2); + cpumask_clear(&cpu_mask); + cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); + irq_set_affinity_hint(res->rx_irq[i], &cpu_mask); } /* For TX MSI */ for (i = 0; i < plat->tx_queues_to_use; i++) { res->tx_irq[i] = pci_irq_vector(pdev, plat->msi_tx_base_vec + i * 2); + cpumask_clear(&cpu_mask); + cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); + irq_set_affinity_hint(res->tx_irq[i], &cpu_mask); } if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX)