Message ID | 20210722110325.371-11-borisp@nvidia.com (mailing list archive) |
---|---|
State | Changes Requested |
Delegated to: | Netdev Maintainers |
Headers | show
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Thu, 22 Jul 2021 11:05:03 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Jul 2021 11:05:02 +0000 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Jul 2021 11:04:57 +0000 From: Boris Pismenny <borisp@nvidia.com> To: <dsahern@gmail.com>, <kuba@kernel.org>, <davem@davemloft.net>, <saeedm@nvidia.com>, <hch@lst.de>, <sagi@grimberg.me>, <axboe@fb.com>, <kbusch@kernel.org>, <viro@zeniv.linux.org.uk>, <edumazet@google.com>, <smalin@marvell.com> CC: <boris.pismenny@gmail.com>, <linux-nvme@lists.infradead.org>, <netdev@vger.kernel.org>, <benishay@nvidia.com>, <ogerlitz@nvidia.com>, <yorayz@nvidia.com>, Boris Pismenny <borisp@mellanox.com>, Or Gerlitz <ogerlitz@mellanox.com>, Yoray Zack <yorayz@mellanox.com> Subject: [PATCH v5 net-next 10/36] net/mlx5: Add 128B CQE for NVMEoTCP offload Date: Thu, 22 Jul 2021 14:02:59 +0300 Message-ID: <20210722110325.371-11-borisp@nvidia.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20210722110325.371-1-borisp@nvidia.com> References: <20210722110325.371-1-borisp@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3c10297a-77ae-4b6d-2fb9-08d94d008ea5 X-MS-TrafficTypeDiagnostic: CH0PR12MB5139: X-Microsoft-Antispam-PRVS: <CH0PR12MB513987865A0A6AE9494C2D60BDE49@CH0PR12MB5139.namprd12.prod.outlook.com> X-MS-Oob-TLC-OOBClassifiers: OLM:2958; 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Series |
nvme-tcp receive and tarnsmit offloads
|
expand
|
Context | Check | Description |
---|---|---|
netdev/apply | fail | Patch does not apply to net-next |
netdev/tree_selection | success | Clearly marked for net-next |
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index a42e47f91327..412d0982ee46 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -794,7 +794,7 @@ struct mlx5_err_cqe { struct mlx5_cqe64 { u8 tls_outer_l3_tunneled; - u8 rsvd0; + u8 nvmetcp; __be16 wqe_id; u8 lro_tcppsh_abort_dupack; u8 lro_min_ttl; @@ -827,6 +827,19 @@ struct mlx5_cqe64 { u8 op_own; }; +struct mlx5e_cqe128 { + __be16 cclen; + __be16 hlen; + union { + __be32 resync_tcp_sn; + __be32 ccoff; + }; + __be16 ccid; + __be16 rsvd8; + u8 rsvd12[52]; + struct mlx5_cqe64 cqe64; +}; + struct mlx5_mini_cqe8 { union { __be32 rx_hash_result; @@ -857,6 +870,27 @@ enum { #define MLX5_MINI_CQE_ARRAY_SIZE 8 +static inline bool cqe_is_nvmeotcp_resync(struct mlx5_cqe64 *cqe) +{ + return ((cqe->nvmetcp >> 6) & 0x1); +} + +static inline bool cqe_is_nvmeotcp_crcvalid(struct mlx5_cqe64 *cqe) +{ + return ((cqe->nvmetcp >> 5) & 0x1); +} + +static inline bool cqe_is_nvmeotcp_zc(struct mlx5_cqe64 *cqe) +{ + return ((cqe->nvmetcp >> 4) & 0x1); +} + +/* check if cqe is zc or crc or resync */ +static inline bool cqe_is_nvmeotcp(struct mlx5_cqe64 *cqe) +{ + return ((cqe->nvmetcp >> 4) & 0x7); +} + static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe) { return (cqe->op_own >> 2) & 0x3;