| Message ID | 20210726194603.14671-6-gerhard@engleder-embedded.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | TSN endpoint Ethernet MAC driver | expand |
| Context | Check | Description |
|---|---|---|
| netdev/cover_letter | success | Link |
| netdev/fixes_present | success | Link |
| netdev/patch_count | success | Link |
| netdev/tree_selection | success | Clearly marked for net-next |
| netdev/subject_prefix | success | Link |
| netdev/cc_maintainers | warning | 1 maintainers not CCed: linux-arm-kernel@lists.infradead.org |
| netdev/source_inline | success | Was 0 now: 0 |
| netdev/verify_signedoff | success | Link |
| netdev/module_param | success | Was 0 now: 0 |
| netdev/build_32bit | success | Errors and warnings before: 0 this patch: 0 |
| netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| netdev/verify_fixes | success | Link |
| netdev/checkpatch | warning | WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? |
| netdev/build_allmodconfig_warn | success | Errors and warnings before: 0 this patch: 0 |
| netdev/header_inline | success | Link |
On Mon, Jul 26, 2021 at 1:46 PM Gerhard Engleder <gerhard@engleder-embedded.com> wrote: > > Combination of Xilinx ZCU104 with Avnet AES-FMC-NETW1-G and TSN endpoint > Ethernet MAC implemented in FPGA. > > Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com> > --- > arch/arm64/boot/dts/xilinx/Makefile | 1 + > arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts | 50 +++++++++++++++++++++ > 2 files changed, 51 insertions(+) > create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts > > diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile > index 11fb4fd3ebd4..d0f94ba8ebac 100644 > --- a/arch/arm64/boot/dts/xilinx/Makefile > +++ b/arch/arm64/boot/dts/xilinx/Makefile > @@ -1,5 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0 > dtb-$(CONFIG_ARCH_ZYNQMP) += avnet-ultra96-rev1.dtb > +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-tsnep.dtb > dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb > dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb > dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts b/arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts > new file mode 100644 > index 000000000000..19e78b483f44 > --- /dev/null > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts > @@ -0,0 +1,50 @@ > +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) > +/* > + * TSN endpoint on Xilinx ZCU104 with Avnet AES-FMC-NETW1-G > + * > + * Copyright (C) 2021 Gerhard Engleder <engleder.gerhard@gmail.com> > + */ > + > +/dts-v1/; > + > +#include "zynqmp-zcu104-revC.dts" > + > +/ { > + model = "TSN endpoint"; > + compatible = "engleder,zynqmp-tsnep", "xlnx,zynqmp-zcu104-revC", > + "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; I don't think this will pass schema validation. In general, do we need a new top-level compatible for every possible FPGA image? Shouldn't this be an overlay? Rob
On Tue, Jul 27, 2021 at 1:41 AM Rob Herring <robh+dt@kernel.org> wrote: > > + compatible = "engleder,zynqmp-tsnep", "xlnx,zynqmp-zcu104-revC", > > + "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; > > I don't think this will pass schema validation. You are right. I did rerun the validation and now I see the error. > In general, do we need a new top-level compatible for every possible > FPGA image? Shouldn't this be an overlay? All the devices I have dealt with so far had just a single FPGA image. There were no dynamic selection of the FPGA image or partial reconfiguration of the FPGA. So the FPGA image could be seen as part of the schematics. In this case the FPGA image stuff shall be in the device tree of the device. For me the question is: Does this combination of evaluation boards with its own FPGA image form a new device? The evaluation platform is based on ZCU104. The difference is not only the FPGA image. Also a FMC extension card with Ethernet PHYs is needed. So also the physical hardware is different. From my point of view it is a separate hardware platform with its own device tree. It's purpose is to show two tsnep Ethernet controllers in action. So far it worked good for me to see the FPGA image as part of the schematics like the list of devices on the SPI bus. No special handling just because an FPGA is used, which in the end is not relevant for the software because software cannot and need not differentiate between normal hardware and FPGA based hardware. But I also understand the view of just another FPGA image for an existing hardware. My goal is to get all necessary stuff, which is needed to run the evaluation platform, into mainline. I must confess, I have not thought about using an overlay. Is it right that overlays are not part of the kernel tree? Gerhard
On Tue, Jul 27, 2021 at 2:11 PM Gerhard Engleder <gerhard@engleder-embedded.com> wrote: > > On Tue, Jul 27, 2021 at 1:41 AM Rob Herring <robh+dt@kernel.org> wrote: > > > + compatible = "engleder,zynqmp-tsnep", "xlnx,zynqmp-zcu104-revC", > > > + "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; > > > > I don't think this will pass schema validation. > > You are right. I did rerun the validation and now I see the error. > > > In general, do we need a new top-level compatible for every possible > > FPGA image? Shouldn't this be an overlay? > > All the devices I have dealt with so far had just a single FPGA image. > There were no dynamic selection of the FPGA image or partial > reconfiguration of the FPGA. So the FPGA image could be seen as part > of the schematics. In this case the FPGA image stuff shall be in the > device tree of the device. For me the question is: Does this combination > of evaluation boards with its own FPGA image form a new device? > > The evaluation platform is based on ZCU104. The difference is not > only the FPGA image. Also a FMC extension card with Ethernet PHYs is > needed. So also the physical hardware is different. Okay, that's enough of a reason for another compatible. You'll have to update the schema. > From my point of view it is a separate hardware platform with its own > device tree. It's purpose is to show two tsnep Ethernet controllers in > action. So far it worked good for me to see the FPGA image as part of > the schematics like the list of devices on the SPI bus. No special handling > just because an FPGA is used, which in the end is not relevant for the > software because software cannot and need not differentiate between > normal hardware and FPGA based hardware. > > But I also understand the view of just another FPGA image for an existing > hardware. > > My goal is to get all necessary stuff, which is needed to run the evaluation > platform, into mainline. I must confess, I have not thought about using an > overlay. Is it right that overlays are not part of the kernel tree? There's some work in progress on it. We can build and apply overlays at build time now, but we haven't added any overlays under /arch. Given the overall h/w is different, it doesn't seem like overlay will buy you anything here. Rob
On Tue, Jul 27, 2021 at 10:18 PM Rob Herring <robh+dt@kernel.org> wrote: > > The evaluation platform is based on ZCU104. The difference is not > > only the FPGA image. Also a FMC extension card with Ethernet PHYs is > > needed. So also the physical hardware is different. > > Okay, that's enough of a reason for another compatible. You'll have to > update the schema. Ok, I will update Documentation/devicetree/bindings/arm/xilinx.yaml. Gerhard
On 7/27/21 10:23 PM, Gerhard Engleder wrote: > On Tue, Jul 27, 2021 at 10:18 PM Rob Herring <robh+dt@kernel.org> wrote: >>> The evaluation platform is based on ZCU104. The difference is not >>> only the FPGA image. Also a FMC extension card with Ethernet PHYs is >>> needed. So also the physical hardware is different. >> >> Okay, that's enough of a reason for another compatible. You'll have to >> update the schema. > > Ok, I will update Documentation/devicetree/bindings/arm/xilinx.yaml. In past we said that we won't be accepting any FPGA description in u-boot/linux projects. I don't think anything has changed from that time and I don't want to end up in situation that we will have a lot of configurations which none else can try and use. Also based on your description where you use evaluation board with FMC card it is far from any product and looks like demonstration configuration. You can add the same fragment to dt binding example which should be enough for everybody to understand how your IP should be described. Thanks, Michal
On Wed, Jul 28, 2021 at 7:10 AM Michal Simek <michal.simek@xilinx.com> wrote: > On 7/27/21 10:23 PM, Gerhard Engleder wrote: > > On Tue, Jul 27, 2021 at 10:18 PM Rob Herring <robh+dt@kernel.org> wrote: > >>> The evaluation platform is based on ZCU104. The difference is not > >>> only the FPGA image. Also a FMC extension card with Ethernet PHYs is > >>> needed. So also the physical hardware is different. > >> > >> Okay, that's enough of a reason for another compatible. You'll have to > >> update the schema. > > > > Ok, I will update Documentation/devicetree/bindings/arm/xilinx.yaml. > > In past we said that we won't be accepting any FPGA description in > u-boot/linux projects. I don't think anything has changed from that time > and I don't want to end up in situation that we will have a lot of > configurations which none else can try and use. I agree that it does not make sense to add configurations that no one else can try and use. The goal is that others can easily try out the IP. I want to provide the FPGA image to others who are interested. It won't be many of course. > Also based on your description where you use evaluation board with FMC > card it is far from any product and looks like demonstration configuration. You are right, it is not product, which is addressed to end users. It is a demonstration configuration for developers. Isn't that valid for all evaluation boards? As a developer I'm very happy if I can do evaluation and development without any vendor tree. I can do that now with the ZCU104. So a big thank you from me for your work! > You can add the same fragment to dt binding example which should be > enough for everybody to understand how your IP should be described. This dt binding example is already there. So a device tree like this won't be accepted? Gerhard
On 7/28/21 10:19 AM, Gerhard Engleder wrote: > On Wed, Jul 28, 2021 at 7:10 AM Michal Simek <michal.simek@xilinx.com> wrote: >> On 7/27/21 10:23 PM, Gerhard Engleder wrote: >>> On Tue, Jul 27, 2021 at 10:18 PM Rob Herring <robh+dt@kernel.org> wrote: >>>>> The evaluation platform is based on ZCU104. The difference is not >>>>> only the FPGA image. Also a FMC extension card with Ethernet PHYs is >>>>> needed. So also the physical hardware is different. >>>> >>>> Okay, that's enough of a reason for another compatible. You'll have to >>>> update the schema. >>> >>> Ok, I will update Documentation/devicetree/bindings/arm/xilinx.yaml. >> >> In past we said that we won't be accepting any FPGA description in >> u-boot/linux projects. I don't think anything has changed from that time >> and I don't want to end up in situation that we will have a lot of >> configurations which none else can try and use. > > I agree that it does not make sense to add configurations that no one else > can try and use. The goal is that others can easily try out the IP. I want to > provide the FPGA image to others who are interested. It won't be many of > course. > >> Also based on your description where you use evaluation board with FMC >> card it is far from any product and looks like demonstration configuration. > > You are right, it is not product, which is addressed to end users. It is a > demonstration configuration for developers. Isn't that valid for all evaluation > boards? As a developer I'm very happy if I can do evaluation and development > without any vendor tree. I can do that now with the ZCU104. So a big thank > you from me for your work! > >> You can add the same fragment to dt binding example which should be >> enough for everybody to understand how your IP should be described. > > This dt binding example is already there. > > So a device tree like this won't be accepted? You have to share to customers bitstream. Likely also boot.bin with PS/PL configuration and other files in it. That's why it will be quite simple to also share them full DT or DT overlay just for your IP in the same image. Till now I didn't hear any strong argument why this should be accepted. Thanks, Michal
On Wed, Jul 28, 2021 at 12:59 PM Michal Simek <michal.simek@xilinx.com> wrote: > >> In past we said that we won't be accepting any FPGA description in > >> u-boot/linux projects. I don't think anything has changed from that time > >> and I don't want to end up in situation that we will have a lot of > >> configurations which none else can try and use. > You have to share to customers bitstream. Likely also boot.bin with > PS/PL configuration and other files in it. That's why it will be quite > simple to also share them full DT or DT overlay just for your IP in the > same image. That's possible of course. > Till now I didn't hear any strong argument why this should be accepted. I want to try a new argument: For new bindings a schema is used. The goal is to ensure that the binding schema and the driver fit together. The validation chain is the following: 1) The binding schema is used to validate the device tree. 2) The device tree is used to "validate" the driver by booting. So the kernel tree needs to contain a device tree which uses the binding to build up the complete validation chain. The validation of the driver against the binding is not possible without a device tree. The only option would be to compare driver and binding manually, which is error prone. If device trees with FPGA descriptions are not allowed in the kernel tree, then the kernel tree will never contain complete validation chains für FPGA based IPs. The validation of bindings for FPGA based IPs has to rely on device trees which are maintained out of tree. It is possible/likely that schema validation is not done out of tree. As a result it is more likely that binding and driver do not fit together for FPGA based IPs. In the end the quality of the support for FPGA based IPs would suffer. I suggest allowing a single device tree with FPGA descriptions for a binding of FPGA based IPs. This will build up the complete validation chain in the kernel tree and ensures that binding and driver fit together. This single device tree would form the reference platform for the FPGA based IP. Gerhard
On 7/28/21 10:51 PM, Gerhard Engleder wrote: > On Wed, Jul 28, 2021 at 12:59 PM Michal Simek <michal.simek@xilinx.com> wrote: >>>> In past we said that we won't be accepting any FPGA description in >>>> u-boot/linux projects. I don't think anything has changed from that time >>>> and I don't want to end up in situation that we will have a lot of >>>> configurations which none else can try and use. >> You have to share to customers bitstream. Likely also boot.bin with >> PS/PL configuration and other files in it. That's why it will be quite >> simple to also share them full DT or DT overlay just for your IP in the >> same image. > > That's possible of course. > >> Till now I didn't hear any strong argument why this should be accepted. > > I want to try a new argument: > > For new bindings a schema is used. The goal is to ensure that the binding > schema and the driver fit together. The validation chain is the following: > 1) The binding schema is used to validate the device tree. > 2) The device tree is used to "validate" the driver by booting. > > So the kernel tree needs to contain a device tree which uses the binding > to build up the complete validation chain. The validation of the driver against > the binding is not possible without a device tree. The only option would be > to compare driver and binding manually, which is error prone. > > If device trees with FPGA descriptions are not allowed in the kernel tree, then > the kernel tree will never contain complete validation chains für FPGA based > IPs. The validation of bindings for FPGA based IPs has to rely on device trees > which are maintained out of tree. It is possible/likely that schema > validation is > not done out of tree. As a result it is more likely that binding and > driver do not > fit together for FPGA based IPs. In the end the quality of the support for FPGA > based IPs would suffer. > > I suggest allowing a single device tree with FPGA descriptions for a binding > of FPGA based IPs. This will build up the complete validation chain in the > kernel tree and ensures that binding and driver fit together. This single device > tree would form the reference platform for the FPGA based IP. This is good theory but the only person who can do this validation is you or your customer who is interested in TSN. I am doing this for quite a long time and even people are giving me commitments that they will support the whole custom board but they stop to do at some point and then silently disappear. Then it is up to me to deal with this and I really don't want to do it. When your driver is merged you should start to do regression testing against linux-next, rc versions. When you convince me that you are regularly doing this for 2 years or so we can restart this discussion. Till that time you can simply keep rebasing one patch with your DT on the top which is quite easy to do and you get all functionality/advantages you are asking about above. Thanks, Michal
On Thu, Jul 29, 2021 at 7:22 AM Michal Simek <michal.simek@xilinx.com> wrote: > On 7/28/21 10:51 PM, Gerhard Engleder wrote: > > On Wed, Jul 28, 2021 at 12:59 PM Michal Simek <michal.simek@xilinx.com> wrote: > >>>> In past we said that we won't be accepting any FPGA description in > >>>> u-boot/linux projects. I don't think anything has changed from that time > >>>> and I don't want to end up in situation that we will have a lot of > >>>> configurations which none else can try and use. > >> You have to share to customers bitstream. Likely also boot.bin with > >> PS/PL configuration and other files in it. That's why it will be quite > >> simple to also share them full DT or DT overlay just for your IP in the > >> same image. > > > > That's possible of course. > > > >> Till now I didn't hear any strong argument why this should be accepted. > > > > I want to try a new argument: > > > > For new bindings a schema is used. The goal is to ensure that the binding > > schema and the driver fit together. The validation chain is the following: > > 1) The binding schema is used to validate the device tree. > > 2) The device tree is used to "validate" the driver by booting. > > > > So the kernel tree needs to contain a device tree which uses the binding > > to build up the complete validation chain. The validation of the driver against > > the binding is not possible without a device tree. The only option would be > > to compare driver and binding manually, which is error prone. > > > > If device trees with FPGA descriptions are not allowed in the kernel tree, then > > the kernel tree will never contain complete validation chains für FPGA based > > IPs. The validation of bindings for FPGA based IPs has to rely on device trees > > which are maintained out of tree. It is possible/likely that schema > > validation is > > not done out of tree. As a result it is more likely that binding and > > driver do not > > fit together for FPGA based IPs. In the end the quality of the support for FPGA > > based IPs would suffer. > > > > I suggest allowing a single device tree with FPGA descriptions for a binding > > of FPGA based IPs. This will build up the complete validation chain in the > > kernel tree and ensures that binding and driver fit together. This single device > > tree would form the reference platform for the FPGA based IP. > > This is good theory but the only person who can do this validation is > you or your customer who is interested in TSN. I am doing this for quite > a long time and even people are giving me commitments that they will > support the whole custom board but they stop to do at some point and > then silently disappear. Then it is up to me to deal with this and I > really don't want to do it. > When your driver is merged you should start to do regression testing > against linux-next, rc versions. When you convince me that you are > regularly doing this for 2 years or so we can restart this discussion. > > Till that time you can simply keep rebasing one patch with your DT on > the top which is quite easy to do and you get all > functionality/advantages you are asking about above. Ok, I give up. Gerhard
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 11fb4fd3ebd4..d0f94ba8ebac 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ZYNQMP) += avnet-ultra96-rev1.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-tsnep.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts b/arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts new file mode 100644 index 000000000000..19e78b483f44 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * TSN endpoint on Xilinx ZCU104 with Avnet AES-FMC-NETW1-G + * + * Copyright (C) 2021 Gerhard Engleder <engleder.gerhard@gmail.com> + */ + +/dts-v1/; + +#include "zynqmp-zcu104-revC.dts" + +/ { + model = "TSN endpoint"; + compatible = "engleder,zynqmp-tsnep", "xlnx,zynqmp-zcu104-revC", + "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; + + amba: axi { + tnsep0: ethernet@a0000000 { + compatible = "engleder,tsnep"; + reg = <0x0 0xa0000000 0x0 0x10000>; + interrupts = <0 89 1>; + interrupt-parent = <&gic>; + local-mac-address = [00 00 00 00 00 00]; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@1 { + reg = <1>; + rxc-skew-ps = <1080>; + }; + }; + + tsnep1: ethernet@a0010000 { + compatible = "engleder,tsnep"; + reg = <0x0 0xa0010000 0x0 0x10000>; + interrupts = <0 90 1>; + interrupt-parent = <&gic>; + local-mac-address = [00 00 00 00 00 00]; + phy-mode = "rgmii"; + phy-handle = <&phy2>; + #address-cells = <1>; + #size-cells = <0>; + phy2: ethernet-phy@1 { + reg = <1>; + rxc-skew-ps = <1080>; + }; + }; + }; +};
Combination of Xilinx ZCU104 with Avnet AES-FMC-NETW1-G and TSN endpoint Ethernet MAC implemented in FPGA. Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com> --- arch/arm64/boot/dts/xilinx/Makefile | 1 + arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts | 50 +++++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts