| Message ID | 20210915064721.5530-4-claudiu.beznea@microchip.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: macb: add support for MII on RGMII interface | expand |
| Context | Check | Description |
|---|---|---|
| netdev/cover_letter | success | Link |
| netdev/fixes_present | success | Link |
| netdev/patch_count | success | Link |
| netdev/tree_selection | success | Guessed tree name to be net-next |
| netdev/subject_prefix | warning | Target tree name not specified in the subject |
| netdev/cc_maintainers | success | CCed 5 of 5 maintainers |
| netdev/source_inline | success | Was 0 now: 0 |
| netdev/verify_signedoff | success | Link |
| netdev/module_param | success | Was 0 now: 0 |
| netdev/build_32bit | success | Errors and warnings before: 25 this patch: 25 |
| netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| netdev/verify_fixes | success | Link |
| netdev/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 24 lines checked |
| netdev/build_allmodconfig_warn | success | Errors and warnings before: 25 this patch: 25 |
| netdev/header_inline | success | Link |
On 15/09/2021 at 08:47, Claudiu Beznea wrote: > Cadence IP has option to enable MII support on RGMII interface. This > could be selected though bit 28 of network control register. This option > is not enabled on all the IP versions thus add a software capability to > be selected by the proper implementation of this IP. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Fine: Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Thanks Claudiu, best regards, Nicolas > --- > drivers/net/ethernet/cadence/macb.h | 3 +++ > drivers/net/ethernet/cadence/macb_main.c | 3 +++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h > index c33e98bfa5e8..5620b97b3482 100644 > --- a/drivers/net/ethernet/cadence/macb.h > +++ b/drivers/net/ethernet/cadence/macb.h > @@ -246,6 +246,8 @@ > #define MACB_SRTSM_OFFSET 15 /* Store Receive Timestamp to Memory */ > #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */ > #define MACB_OSSMODE_SIZE 1 > +#define MACB_MIIONRGMII_OFFSET 28 /* MII Usage on RGMII Interface */ > +#define MACB_MIIONRGMII_SIZE 1 > > /* Bitfields in NCFGR */ > #define MACB_SPD_OFFSET 0 /* Speed */ > @@ -713,6 +715,7 @@ > #define MACB_CAPS_GEM_HAS_PTP 0x00000040 > #define MACB_CAPS_BD_RD_PREFETCH 0x00000080 > #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 > +#define MACB_CAPS_MIIONRGMII 0x00000200 > #define MACB_CAPS_CLK_HW_CHG 0x04000000 > #define MACB_CAPS_MACB_IS_EMAC 0x08000000 > #define MACB_CAPS_FIFO_MODE 0x10000000 > diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c > index d13fb1d31821..cdf3e35b5b33 100644 > --- a/drivers/net/ethernet/cadence/macb_main.c > +++ b/drivers/net/ethernet/cadence/macb_main.c > @@ -684,6 +684,9 @@ static void macb_mac_config(struct phylink_config *config, unsigned int mode, > } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) { > ctrl |= GEM_BIT(PCSSEL); > ncr |= GEM_BIT(ENABLE_HS_MAC); > + } else if (bp->caps & MACB_CAPS_MIIONRGMII && > + bp->phy_interface == PHY_INTERFACE_MODE_MII) { > + ncr |= MACB_BIT(MIIONRGMII); > } > } > >
On Wed, Sep 15, 2021 at 09:47:21AM +0300, Claudiu Beznea wrote: > Cadence IP has option to enable MII support on RGMII interface. This > could be selected though bit 28 of network control register. This option > is not enabled on all the IP versions thus add a software capability to > be selected by the proper implementation of this IP. Hi Claudiu You are adding a feature without a user. That is generally not accepted. Could you please also extend one of the macb_config structs to make use of this? Thanks Andrew
Hi Andrew, On 16.09.2021 16:03, Andrew Lunn wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On Wed, Sep 15, 2021 at 09:47:21AM +0300, Claudiu Beznea wrote: >> Cadence IP has option to enable MII support on RGMII interface. This >> could be selected though bit 28 of network control register. This option >> is not enabled on all the IP versions thus add a software capability to >> be selected by the proper implementation of this IP. > > Hi Claudiu > > You are adding a feature without a user. That is generally not > accepted. That's true. For whatever reason I haven't added proper flags to macb_config objects. I've send a new version with updates. Thank you for your review, Claudiu Beznea > Could you please also extend one of the macb_config structs > to make use of this? > > Thanks > Andrew >
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index c33e98bfa5e8..5620b97b3482 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -246,6 +246,8 @@ #define MACB_SRTSM_OFFSET 15 /* Store Receive Timestamp to Memory */ #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */ #define MACB_OSSMODE_SIZE 1 +#define MACB_MIIONRGMII_OFFSET 28 /* MII Usage on RGMII Interface */ +#define MACB_MIIONRGMII_SIZE 1 /* Bitfields in NCFGR */ #define MACB_SPD_OFFSET 0 /* Speed */ @@ -713,6 +715,7 @@ #define MACB_CAPS_GEM_HAS_PTP 0x00000040 #define MACB_CAPS_BD_RD_PREFETCH 0x00000080 #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 +#define MACB_CAPS_MIIONRGMII 0x00000200 #define MACB_CAPS_CLK_HW_CHG 0x04000000 #define MACB_CAPS_MACB_IS_EMAC 0x08000000 #define MACB_CAPS_FIFO_MODE 0x10000000 diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index d13fb1d31821..cdf3e35b5b33 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -684,6 +684,9 @@ static void macb_mac_config(struct phylink_config *config, unsigned int mode, } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) { ctrl |= GEM_BIT(PCSSEL); ncr |= GEM_BIT(ENABLE_HS_MAC); + } else if (bp->caps & MACB_CAPS_MIIONRGMII && + bp->phy_interface == PHY_INTERFACE_MODE_MII) { + ncr |= MACB_BIT(MIIONRGMII); } }
Cadence IP has option to enable MII support on RGMII interface. This could be selected though bit 28 of network control register. This option is not enabled on all the IP versions thus add a software capability to be selected by the proper implementation of this IP. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- drivers/net/ethernet/cadence/macb.h | 3 +++ drivers/net/ethernet/cadence/macb_main.c | 3 +++ 2 files changed, 6 insertions(+)