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[v2,2/4] net: macb: align for OSSMODE offset

Message ID 20210917132615.16183-3-claudiu.beznea@microchip.com (mailing list archive)
State Accepted
Commit d7b3485f1c2b917328890ba28f4e7cac4b98ca1e
Delegated to: Netdev Maintainers
Headers show
Series net: macb: add support for MII on RGMII interface | expand

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netdev/cc_maintainers success CCed 5 of 5 maintainers
netdev/source_inline success Was 0 now: 0
netdev/verify_signedoff success Link
netdev/module_param success Was 0 now: 0
netdev/build_32bit success Errors and warnings before: 25 this patch: 25
netdev/kdoc success Errors and warnings before: 0 this patch: 0
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netdev/checkpatch success total: 0 errors, 0 warnings, 0 checks, 8 lines checked
netdev/build_allmodconfig_warn success Errors and warnings before: 25 this patch: 25
netdev/header_inline success Link

Commit Message

Claudiu Beznea Sept. 17, 2021, 1:26 p.m. UTC 
Align for OSSMODE offset.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
---
 drivers/net/ethernet/cadence/macb.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index d1e0e116b976..c33e98bfa5e8 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -244,7 +244,7 @@ 
 #define MACB_TZQ_OFFSET		12 /* Transmit zero quantum pause frame */
 #define MACB_TZQ_SIZE		1
 #define MACB_SRTSM_OFFSET	15 /* Store Receive Timestamp to Memory */
-#define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
+#define MACB_OSSMODE_OFFSET	24 /* Enable One Step Synchro Mode */
 #define MACB_OSSMODE_SIZE	1
 
 /* Bitfields in NCFGR */