| Message ID | 20210929115226.1383925-1-vladimir.oltean@nxp.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [devicetree] arm64: dts: ls1028a: mark internal links between Felix and ENETC as capable of flow control | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Not a local patch |
On Wed, Sep 29, 2021 at 02:52:26PM +0300, Vladimir Oltean wrote: > The internal Ethernet switch suffers from erratum A-050484 ("Ethernet > flow control not functional on L2 switch NPI port when XFH is used"). > XFH stands for "Extraction Frame Header" - which basically means the > default "ocelot" DSA tagging protocol. > > However, the switch supports one other tagging protocol - "ocelot-8021q", > and this is not subject to the erratum above. So describe the hardware > ability to pass PAUSE frames in the device tree, and let the driver > figure out whether it should use flow control on the CPU port or not, > depending on whether the "ocelot" or "ocelot-8021q" tagging protocol is > being used. > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Applied, thanks!
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 343ecf0e8973..71e5cdd931ee 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -1025,6 +1025,7 @@ enetc_port2: ethernet@0,2 { fixed-link { speed = <2500>; full-duplex; + pause; }; }; @@ -1083,6 +1084,7 @@ mscc_felix_port4: port@4 { fixed-link { speed = <2500>; full-duplex; + pause; }; }; @@ -1094,6 +1096,7 @@ mscc_felix_port5: port@5 { fixed-link { speed = <1000>; full-duplex; + pause; }; }; }; @@ -1108,6 +1111,7 @@ enetc_port3: ethernet@0,6 { fixed-link { speed = <1000>; full-duplex; + pause; }; };
The internal Ethernet switch suffers from erratum A-050484 ("Ethernet flow control not functional on L2 switch NPI port when XFH is used"). XFH stands for "Extraction Frame Header" - which basically means the default "ocelot" DSA tagging protocol. However, the switch supports one other tagging protocol - "ocelot-8021q", and this is not subject to the erratum above. So describe the hardware ability to pass PAUSE frames in the device tree, and let the driver figure out whether it should use flow control on the CPU port or not, depending on whether the "ocelot" or "ocelot-8021q" tagging protocol is being used. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 ++++ 1 file changed, 4 insertions(+)