From patchwork Fri Oct 1 16:43:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12531061 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 524EBC433F5 for ; Fri, 1 Oct 2021 16:43:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3B28F6124D for ; Fri, 1 Oct 2021 16:43:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355259AbhJAQpZ (ORCPT ); Fri, 1 Oct 2021 12:45:25 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:53132 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1355258AbhJAQpY (ORCPT ); Fri, 1 Oct 2021 12:45:24 -0400 X-IronPort-AV: E=Sophos;i="5.85,339,1624287600"; d="scan'208";a="95827564" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 02 Oct 2021 01:43:39 +0900 Received: from localhost.localdomain (unknown [10.226.92.36]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id AF6BC400A89E; Sat, 2 Oct 2021 01:43:36 +0900 (JST) From: Biju Das To: "David S. Miller" , Jakub Kicinski Cc: Biju Das , Sergei Shtylyov , Geert Uytterhoeven , Sergey Shtylyov , Adam Ford , Andrew Lunn , Yuusuke Ashizuka , Yoshihiro Shimoda , netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH 8/8] ravb: Fillup ravb_set_features_gbeth() stub Date: Fri, 1 Oct 2021 17:43:05 +0100 Message-Id: <20211001164305.8999-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211001164305.8999-1-biju.das.jz@bp.renesas.com> References: <20211001164305.8999-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Fillup ravb_set_features_gbeth() function to support RZ/G2L. Also set the net_hw_features bits supported by GbEthernet Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- RFC->v1: * moved stats to patch #7. * Added CSR0 initilization --- drivers/net/ethernet/renesas/ravb.h | 38 ++++++++++++++++++++++++ drivers/net/ethernet/renesas/ravb_main.c | 34 ++++++++++++++++++++- 2 files changed, 71 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index 04aedde608e3..11a40ea0dfd2 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -206,6 +206,9 @@ enum ravb_reg { CXR55 = 0x0768, /* RZ/G2L only */ CXR56 = 0x0770, /* RZ/G2L only */ MAFCR = 0x0778, + CSR0 = 0x0800, /* RZ/G2L only */ + CSR1 = 0x0804, /* RZ/G2L only */ + CSR2 = 0x0808, /* RZ/G2L only */ }; @@ -966,6 +969,41 @@ enum CXR31_BIT { CXR31_SEL_LINK1 = 0x00000008, }; +enum CSR0_BIT { + CSR0_TPE = 0x00000010, + CSR0_RPE = 0x00000020, +}; + +enum CSR1_BIT { + CSR1_TIP4 = 0x00000001, + CSR1_TTCP4 = 0x00000010, + CSR1_TUDP4 = 0x00000020, + CSR1_TICMP4 = 0x00000040, + CSR1_TTCP6 = 0x00100000, + CSR1_TUDP6 = 0x00200000, + CSR1_TICMP6 = 0x00400000, + CSR1_THOP = 0x01000000, + CSR1_TROUT = 0x02000000, + CSR1_TAHD = 0x04000000, + CSR1_TDHD = 0x08000000, + CSR1_ALL = 0x0F700071, +}; + +enum CSR2_BIT { + CSR2_RIP4 = 0x00000001, + CSR2_RTCP4 = 0x00000010, + CSR2_RUDP4 = 0x00000020, + CSR2_RICMP4 = 0x00000040, + CSR2_RTCP6 = 0x00100000, + CSR2_RUDP6 = 0x00200000, + CSR2_RICMP6 = 0x00400000, + CSR2_RHOP = 0x01000000, + CSR2_RROUT = 0x02000000, + CSR2_RAHD = 0x04000000, + CSR2_RDHD = 0x08000000, + CSR2_ALL = 0x0F700071, +}; + #define DBAT_ENTRY_NUM 22 #define RX_QUEUE_OFFSET 4 #define NUM_RX_QUEUE 2 diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index ee4153831158..a2c07efdb2f5 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -533,6 +533,7 @@ static void ravb_emac_init_gbeth(struct net_device *ndev) /* E-MAC status register clear */ ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); + ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); /* E-MAC interrupt enable register */ ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); @@ -2330,7 +2331,37 @@ static void ravb_set_rx_csum(struct net_device *ndev, bool enable) static int ravb_set_features_gbeth(struct net_device *ndev, netdev_features_t features) { - /* Place holder */ + netdev_features_t changed = features ^ ndev->features; + int error; + u32 csr0; + + csr0 = ravb_read(ndev, CSR0); + ravb_write(ndev, csr0 & ~(CSR0_RPE | CSR0_TPE), CSR0); + error = ravb_wait(ndev, CSR0, CSR0_RPE | CSR0_TPE, 0); + if (error) { + ravb_write(ndev, csr0, CSR0); + return error; + } + + if (changed & NETIF_F_RXCSUM) { + if (features & NETIF_F_RXCSUM) + ravb_write(ndev, CSR2_ALL, CSR2); + else + ravb_write(ndev, 0, CSR2); + } + + if (changed & NETIF_F_HW_CSUM) { + if (features & NETIF_F_HW_CSUM) { + ravb_write(ndev, CSR1_ALL, CSR1); + ndev->features |= NETIF_F_CSUM_MASK; + } else { + ravb_write(ndev, 0, CSR1); + } + } + ravb_write(ndev, csr0, CSR0); + + ndev->features = features; + return 0; } @@ -2473,6 +2504,7 @@ static const struct ravb_hw_info gbeth_hw_info = { .set_feature = ravb_set_features_gbeth, .dmac_init = ravb_dmac_init_gbeth, .emac_init = ravb_emac_init_gbeth, + .net_hw_features = (NETIF_F_HW_CSUM | NETIF_F_RXCSUM), .gstrings_stats = ravb_gstrings_stats_gbeth, .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth),