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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id z8sm9462678ejd.94.2021.10.06.15.36.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Oct 2021 15:36:33 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next PATCH 05/13] net: dsa: qca8k: add mac_power_sel support Date: Thu, 7 Oct 2021 00:35:55 +0200 Message-Id: <20211006223603.18858-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211006223603.18858-1-ansuelsmth@gmail.com> References: <20211006223603.18858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add missing mac power sel support needed for some switch that requires additional setup. ar8327 have a different setup than 8337. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 27 +++++++++++++++++++++++++++ drivers/net/dsa/qca8k.h | 5 +++++ 2 files changed, 32 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index bda5a9bf4f52..5bce7ac4dea7 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -950,6 +950,29 @@ qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv) return 0; } +static int +qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) +{ + struct device_node *node = priv->dev->of_node; + u32 mask = 0; + int ret = 0; + + if (of_property_read_bool(node, "qca,rgmii0-1-8v")) + mask |= QCA8K_MAC_PWR_RGMII0_1_8V; + + if (of_property_read_bool(node, "qca,rgmii56-1-8v")) + mask |= QCA8K_MAC_PWR_RGMII1_1_8V; + + if (mask) { + ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL, + QCA8K_MAC_PWR_RGMII0_1_8V | + QCA8K_MAC_PWR_RGMII1_1_8V, + mask); + } + + return ret; +} + static int qca8k_setup(struct dsa_switch *ds) { @@ -979,6 +1002,10 @@ qca8k_setup(struct dsa_switch *ds) if (ret) return ret; + ret = qca8k_setup_mac_pwr_sel(priv); + if (ret) + return ret; + /* Enable CPU Port */ ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index ed3b05ad6745..fc7db94cc0c9 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -100,6 +100,11 @@ #define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22) #define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22) +/* MAC_PWR_SEL registers */ +#define QCA8K_REG_MAC_PWR_SEL 0x0e4 +#define QCA8K_MAC_PWR_RGMII1_1_8V BIT(18) +#define QCA8K_MAC_PWR_RGMII0_1_8V BIT(19) + /* EEE control registers */ #define QCA8K_REG_EEE_CTRL 0x100 #define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)