diff mbox series

[net-next,v3,02/13] net: dsa: qca8k: add support for sgmii falling edge

Message ID 20211010015603.24483-3-ansuelsmth@gmail.com (mailing list archive)
State Superseded
Delegated to: Netdev Maintainers
Headers show
Series Multiple improvement for qca8337 switch | expand

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netdev/fixes_present success Fixes tag not required for -next series
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netdev/tree_selection success Clearly marked for net-next
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netdev/source_inline success Was 0 now: 0
netdev/verify_signedoff success Signed-off-by tag matches author and committer
netdev/module_param success Was 0 now: 0
netdev/build_32bit success Errors and warnings before: 0 this patch: 0
netdev/kdoc success Errors and warnings before: 0 this patch: 0
netdev/verify_fixes success No Fixes tag
netdev/checkpatch warning WARNING: line length of 81 exceeds 80 columns WARNING: line length of 82 exceeds 80 columns
netdev/build_allmodconfig_warn success Errors and warnings before: 0 this patch: 0
netdev/header_inline success No static functions without inline keyword in header files

Commit Message

Christian Marangi Oct. 10, 2021, 1:55 a.m. UTC 
Add support for this in the qca8k driver. Also add support for SGMII
rx/tx clock falling edge. This is only present for pad0, pad5 and
pad6 have these bit reserved from Documentation. Add a comment that this
is hardcoded to PAD0 as qca8327/28/34/37 have an unique sgmii line and
setting falling in port0 applies to both configuration with sgmii used
for port0 or port6.

Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/net/dsa/qca8k.c | 25 +++++++++++++++++++++++++
 drivers/net/dsa/qca8k.h |  3 +++
 2 files changed, 28 insertions(+)

Comments

kernel test robot Oct. 10, 2021, 6:12 a.m. UTC | #1 
Hi Ansuel,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on net-next/master]

url:    https://github.com/0day-ci/linux/commits/Ansuel-Smith/Multiple-improvement-for-qca8337-switch/20211010-095850
base:   https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git 7932d53162dc6550fc56b013da32c0975784647c
config: x86_64-randconfig-a012-20211010 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 903b30fea21f99d8f48fde4defcc838970e30ee1)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/b46afc1d065f0d5add5ea33eae1bf90247ae64c3
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ansuel-Smith/Multiple-improvement-for-qca8337-switch/20211010-095850
        git checkout b46afc1d065f0d5add5ea33eae1bf90247ae64c3
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/net/dsa/qca8k.c:1285:23: warning: result of comparison of constant 5099574 with expression of type 'u8' (aka 'unsigned char') is always false [-Wtautological-constant-out-of-range-compare]
                       priv->switch_id == PHY_ID_QCA8337)
                       ~~~~~~~~~~~~~~~ ^  ~~~~~~~~~~~~~~
   drivers/net/dsa/qca8k.c:1284:23: warning: result of comparison of constant 5099572 with expression of type 'u8' (aka 'unsigned char') is always false [-Wtautological-constant-out-of-range-compare]
                   if (priv->switch_id == PHY_ID_QCA8327 ||
                       ~~~~~~~~~~~~~~~ ^  ~~~~~~~~~~~~~~
   2 warnings generated.


vim +1285 drivers/net/dsa/qca8k.c

  1169	
  1170	static void
  1171	qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  1172				 const struct phylink_link_state *state)
  1173	{
  1174		struct qca8k_priv *priv = ds->priv;
  1175		struct dsa_port *dp;
  1176		u32 reg, val;
  1177		int ret;
  1178	
  1179		switch (port) {
  1180		case 0: /* 1st CPU port */
  1181			if (state->interface != PHY_INTERFACE_MODE_RGMII &&
  1182			    state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
  1183			    state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
  1184			    state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
  1185			    state->interface != PHY_INTERFACE_MODE_SGMII)
  1186				return;
  1187	
  1188			reg = QCA8K_REG_PORT0_PAD_CTRL;
  1189			break;
  1190		case 1:
  1191		case 2:
  1192		case 3:
  1193		case 4:
  1194		case 5:
  1195			/* Internal PHY, nothing to do */
  1196			return;
  1197		case 6: /* 2nd CPU port / external PHY */
  1198			if (state->interface != PHY_INTERFACE_MODE_RGMII &&
  1199			    state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
  1200			    state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
  1201			    state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
  1202			    state->interface != PHY_INTERFACE_MODE_SGMII &&
  1203			    state->interface != PHY_INTERFACE_MODE_1000BASEX)
  1204				return;
  1205	
  1206			reg = QCA8K_REG_PORT6_PAD_CTRL;
  1207			break;
  1208		default:
  1209			dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
  1210			return;
  1211		}
  1212	
  1213		if (port != 6 && phylink_autoneg_inband(mode)) {
  1214			dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
  1215				__func__);
  1216			return;
  1217		}
  1218	
  1219		switch (state->interface) {
  1220		case PHY_INTERFACE_MODE_RGMII:
  1221			/* RGMII mode means no delay so don't enable the delay */
  1222			qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
  1223			break;
  1224		case PHY_INTERFACE_MODE_RGMII_ID:
  1225		case PHY_INTERFACE_MODE_RGMII_TXID:
  1226		case PHY_INTERFACE_MODE_RGMII_RXID:
  1227			/* RGMII_ID needs internal delay. This is enabled through
  1228			 * PORT5_PAD_CTRL for all ports, rather than individual port
  1229			 * registers
  1230			 */
  1231			qca8k_write(priv, reg,
  1232				    QCA8K_PORT_PAD_RGMII_EN |
  1233				    QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) |
  1234				    QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) |
  1235				    QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
  1236				    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
  1237			/* QCA8337 requires to set rgmii rx delay */
  1238			if (priv->switch_id == QCA8K_ID_QCA8337)
  1239				qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
  1240					    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
  1241			break;
  1242		case PHY_INTERFACE_MODE_SGMII:
  1243		case PHY_INTERFACE_MODE_1000BASEX:
  1244			dp = dsa_to_port(ds, port);
  1245	
  1246			/* Enable SGMII on the port */
  1247			qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
  1248	
  1249			/* Enable/disable SerDes auto-negotiation as necessary */
  1250			ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
  1251			if (ret)
  1252				return;
  1253			if (phylink_autoneg_inband(mode))
  1254				val &= ~QCA8K_PWS_SERDES_AEN_DIS;
  1255			else
  1256				val |= QCA8K_PWS_SERDES_AEN_DIS;
  1257			qca8k_write(priv, QCA8K_REG_PWS, val);
  1258	
  1259			/* Configure the SGMII parameters */
  1260			ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
  1261			if (ret)
  1262				return;
  1263	
  1264			val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
  1265				QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
  1266	
  1267			if (dsa_is_cpu_port(ds, port)) {
  1268				/* CPU port, we're talking to the CPU MAC, be a PHY */
  1269				val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
  1270				val |= QCA8K_SGMII_MODE_CTRL_PHY;
  1271			} else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
  1272				val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
  1273				val |= QCA8K_SGMII_MODE_CTRL_MAC;
  1274			} else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
  1275				val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
  1276				val |= QCA8K_SGMII_MODE_CTRL_BASEX;
  1277			}
  1278	
  1279			qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
  1280	
  1281			/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
  1282			 * falling edge is set writing in the PORT0 PAD reg
  1283			 */
  1284			if (priv->switch_id == PHY_ID_QCA8327 ||
> 1285			    priv->switch_id == PHY_ID_QCA8337)
  1286				reg = QCA8K_REG_PORT0_PAD_CTRL;
  1287	
  1288			val = 0;
  1289	
  1290			/* SGMII Clock phase configuration */
  1291			if (of_property_read_bool(dp->dn, "qca,sgmii-rxclk-falling-edge"))
  1292				val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
  1293	
  1294			if (of_property_read_bool(dp->dn, "qca,sgmii-txclk-falling-edge"))
  1295				val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
  1296	
  1297			if (val)
  1298				ret = qca8k_rmw(priv, reg,
  1299						QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
  1300						QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
  1301						val);
  1302			break;
  1303		default:
  1304			dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
  1305				phy_modes(state->interface), port);
  1306			return;
  1307		}
  1308	}
  1309	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff mbox series

Patch

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index a892b897cd0d..863eeac6eace 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1172,6 +1172,7 @@  qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 			 const struct phylink_link_state *state)
 {
 	struct qca8k_priv *priv = ds->priv;
+	struct dsa_port *dp;
 	u32 reg, val;
 	int ret;
 
@@ -1240,6 +1241,8 @@  qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 		break;
 	case PHY_INTERFACE_MODE_SGMII:
 	case PHY_INTERFACE_MODE_1000BASEX:
+		dp = dsa_to_port(ds, port);
+
 		/* Enable SGMII on the port */
 		qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
 
@@ -1274,6 +1277,28 @@  qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 		}
 
 		qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
+
+		/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
+		 * falling edge is set writing in the PORT0 PAD reg
+		 */
+		if (priv->switch_id == PHY_ID_QCA8327 ||
+		    priv->switch_id == PHY_ID_QCA8337)
+			reg = QCA8K_REG_PORT0_PAD_CTRL;
+
+		val = 0;
+
+		/* SGMII Clock phase configuration */
+		if (of_property_read_bool(dp->dn, "qca,sgmii-rxclk-falling-edge"))
+			val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
+
+		if (of_property_read_bool(dp->dn, "qca,sgmii-txclk-falling-edge"))
+			val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
+
+		if (val)
+			ret = qca8k_rmw(priv, reg,
+					QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
+					QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
+					val);
 		break;
 	default:
 		dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index fc7db94cc0c9..3fded69a6839 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -35,6 +35,9 @@ 
 #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK		GENMASK(15, 8)
 #define   QCA8K_MASK_CTRL_DEVICE_ID(x)			((x) >> 8)
 #define QCA8K_REG_PORT0_PAD_CTRL			0x004
+#define   QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG		BIT(31)
+#define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE	BIT(19)
+#define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE	BIT(18)
 #define QCA8K_REG_PORT5_PAD_CTRL			0x008
 #define QCA8K_REG_PORT6_PAD_CTRL			0x00c
 #define   QCA8K_PORT_PAD_RGMII_EN			BIT(26)