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Thu, 14 Oct 2021 17:02:59 +0000 From: Ioana Ciornei To: davem@davemloft.net, kuba@kernel.org Cc: youri.querry_1@nxp.com, leoyang.li@nxp.com, netdev@vger.kernel.org, Ioana Ciornei Subject: [PATCH net-next 2/5] soc: fsl: dpio: add support for irq coalescing per software portal Date: Thu, 14 Oct 2021 20:02:12 +0300 Message-Id: <20211014170215.132687-3-ioana.ciornei@nxp.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211014170215.132687-1-ioana.ciornei@nxp.com> References: <20211014170215.132687-1-ioana.ciornei@nxp.com> X-ClientProxiedBy: AM8P190CA0029.EURP190.PROD.OUTLOOK.COM (2603:10a6:20b:219::34) To AM4PR0401MB2308.eurprd04.prod.outlook.com (2603:10a6:200:4f::13) MIME-Version: 1.0 Received: from yoga-910.localhost (188.26.184.231) by AM8P190CA0029.EURP190.PROD.OUTLOOK.COM (2603:10a6:20b:219::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15 via Frontend Transport; Thu, 14 Oct 2021 17:02:58 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 39aa587f-eb51-489c-462b-08d98f347982 X-MS-TrafficTypeDiagnostic: AM0PR04MB5825: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:179; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lap5Z/PC3wdHe8ZX+cS9q5HIxX9ny5EELtPFfvv77W2KxmQWXD0v4pLus8uM6Cfumvkd05y5F2lxKXjOu5CsixOUpSgLpETvyvrAHkZWFE37lSsSWyg9fmfS8+ZCw/JUlnfW/CWFdgFoZkD3Mj5GzWivWuc3WwamykK8hX8vmZnW3crHaGNLDR0/0WACpa89Y6Ssv283jXwSITAn7NhI1zcV/6IR5/2Zdk8dPNRq37LRe2n1g1ud8c0ns4wyxY3TslsPLUmnJ+8KWMlNin+bFk1uSc+o8aMaFaDrnBqtK/e5rVyl0mlXx5PGd8DTGNoVVVn/3cKr1LpT3iN8qt6zXpVw+exed+d6244k35TdT6MJbehUaQ3YdViESbE7C6PUZUCOUt0oZ2cZmGhxKhjGrKp+QINlLMV5j6DOOfkQkbxJ/XZC3X8p66U/YyhRTiP+J99RSVlbhgIsGBv59wX4LncfoLsh6UGe80HQJXznQnSWei7rdhR4CQKZjhlkPuzkY5pmDGosfWka0dcChCwM/zIc8D6UE9ViL5uhoZi8lhKyNrAqVY9Kq5Wt+mrEusXh3xLuTLFmS5rfTxEHVZ2MszCc0mvuQfMAFyFhfjW8kT1JJqcdVe2lBQ9AyVzgu+Ets83ctIpe1Et+r/05e8dyhHBe6K9VQyUy1I42lV5wlnldzhDxQiEvGWvx0A+8GptrNFOEPpciHPrY4lvaHEyCwd56uuyCyt49R+nF97vgFsSP7yyzgeM4zNx3zTcroECT6Q+z7bg/I0wF1JAy2z/UnCAKmFDUalqY2M5wDDeR0+/bEvgMHnVtCzsg1/AecemOVbe8EhCFB9jpWW9/sxvQ6HLYhl4aceDg1T6uIXMdDWB1ZMJ1AaqG+CT3OKIlwzoP2gjmw36mWwxfT1JVTprHfdLJ+AIS38dN5kGRwtCn0azkHal1cnRQffZ3Z68ZPxV5rkR+IHmAoenr+4BAX0KMe79EvGoIvM4oh0ru+qDkDUPBrfWuN8LLMo91LMk3Kf/3IZzBxNqXK/iOwMw3BbwcWaTTgCzNkPADj8Ckz0tdjxYH0iOKe4qsKhKNX1wpOR8Hi60t4yMfX7KwuLwrYF58bQtVIlsIZICx84APXmhy9esWpZBCH5NrUaAFSbZywIC0kXYUT/SVoskIYj5Wrz5nYXZfaQZ743dJDrMiS5MoEPvUMjxCKZ6SPyrMkpM+Ex+xXjdEHalak+cpDK15YbfrlYjbafQ0FaixP9AwLkriS1665RsQe9WcvKZCl6REIG4VpycVjWGbXerW+x0rsM8tgnizyxlRAiPhpdBoz/5ENTDzmaenwkHV3m6DF0PEge6I X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 39aa587f-eb51-489c-462b-08d98f347982 X-MS-Exchange-CrossTenant-AuthSource: AM4PR0401MB2308.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2021 17:02:59.1517 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: gK77vIrqcb0xkBquONbP8p+s5oqYh2uBujnt+utP4JqFJes7a9IuLhqDZkGIiM1Kt38GeSMT9uCTBZf3hV7E8Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5825 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org In DPAA2 based SoCs, the IRQ coalesing support per software portal has 2 configurable parameters: - the IRQ timeout period (QBMAN_CINH_SWP_ITPR): how many 256 QBMAN cycles need to pass until a dequeue interrupt is asserted. - the IRQ threshold (QBMAN_CINH_SWP_DQRR_ITR): how many dequeue responses in the DQRR ring would generate an IRQ. Add support for setting up and querying these IRQ coalescing related parameters. Signed-off-by: Ioana Ciornei --- drivers/soc/fsl/dpio/dpio-service.c | 37 ++++++++++++++++++ drivers/soc/fsl/dpio/qbman-portal.c | 59 +++++++++++++++++++++++++++++ drivers/soc/fsl/dpio/qbman-portal.h | 11 ++++++ include/soc/fsl/dpaa2-io.h | 4 ++ 4 files changed, 111 insertions(+) diff --git a/drivers/soc/fsl/dpio/dpio-service.c b/drivers/soc/fsl/dpio/dpio-service.c index 2acbb96c5e45..44fafed045ca 100644 --- a/drivers/soc/fsl/dpio/dpio-service.c +++ b/drivers/soc/fsl/dpio/dpio-service.c @@ -114,6 +114,7 @@ struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc, struct device *dev) { struct dpaa2_io *obj = kmalloc(sizeof(*obj), GFP_KERNEL); + u32 qman_256_cycles_per_ns; if (!obj) return NULL; @@ -129,6 +130,13 @@ struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc, obj->swp_desc.cinh_bar = obj->dpio_desc.regs_cinh; obj->swp_desc.qman_clk = obj->dpio_desc.qman_clk; obj->swp_desc.qman_version = obj->dpio_desc.qman_version; + + /* Compute how many 256 QBMAN cycles fit into one ns. This is because + * the interrupt timeout period register needs to be specified in QBMAN + * clock cycles in increments of 256. + */ + qman_256_cycles_per_ns = 256000 / (obj->swp_desc.qman_clk / 1000000); + obj->swp_desc.qman_256_cycles_per_ns = qman_256_cycles_per_ns; obj->swp = qbman_swp_init(&obj->swp_desc); if (!obj->swp) { @@ -780,3 +788,32 @@ int dpaa2_io_query_bp_count(struct dpaa2_io *d, u16 bpid, u32 *num) return 0; } EXPORT_SYMBOL_GPL(dpaa2_io_query_bp_count); + +/** + * dpaa2_io_set_irq_coalescing() - Set new IRQ coalescing values + * @d: the given DPIO object + * @irq_holdoff: interrupt holdoff (timeout) period in us + * + * Return 0 for success, or negative error code on error. + */ +int dpaa2_io_set_irq_coalescing(struct dpaa2_io *d, u32 irq_holdoff) +{ + struct qbman_swp *swp = d->swp; + + return qbman_swp_set_irq_coalescing(swp, swp->dqrr.dqrr_size - 1, + irq_holdoff); +} +EXPORT_SYMBOL(dpaa2_io_set_irq_coalescing); + +/** + * dpaa2_io_get_irq_coalescing() - Get the current IRQ coalescing parameters + * @d: the given DPIO object + * @irq_holdoff: interrupt holdoff (timeout) period in us + */ +void dpaa2_io_get_irq_coalescing(struct dpaa2_io *d, u32 *irq_holdoff) +{ + struct qbman_swp *swp = d->swp; + + qbman_swp_get_irq_coalescing(swp, NULL, irq_holdoff); +} +EXPORT_SYMBOL(dpaa2_io_get_irq_coalescing); diff --git a/drivers/soc/fsl/dpio/qbman-portal.c b/drivers/soc/fsl/dpio/qbman-portal.c index f13da4d7d1c5..d3c58df6240d 100644 --- a/drivers/soc/fsl/dpio/qbman-portal.c +++ b/drivers/soc/fsl/dpio/qbman-portal.c @@ -29,6 +29,7 @@ #define QBMAN_CINH_SWP_EQCR_AM_RT 0x980 #define QBMAN_CINH_SWP_RCR_AM_RT 0x9c0 #define QBMAN_CINH_SWP_DQPI 0xa00 +#define QBMAN_CINH_SWP_DQRR_ITR 0xa80 #define QBMAN_CINH_SWP_DCAP 0xac0 #define QBMAN_CINH_SWP_SDQCR 0xb00 #define QBMAN_CINH_SWP_EQCR_AM_RT2 0xb40 @@ -38,6 +39,7 @@ #define QBMAN_CINH_SWP_IER 0xe40 #define QBMAN_CINH_SWP_ISDR 0xe80 #define QBMAN_CINH_SWP_IIR 0xec0 +#define QBMAN_CINH_SWP_ITPR 0xf40 /* CENA register offsets */ #define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((u32)(n) << 6)) @@ -355,6 +357,9 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) & p->eqcr.pi_ci_mask; p->eqcr.available = p->eqcr.pi_ring_size; + /* Initialize the software portal with a irq timeout period of 0us */ + qbman_swp_set_irq_coalescing(p, p->dqrr.dqrr_size - 1, 0); + return p; } @@ -1796,3 +1801,57 @@ u32 qbman_bp_info_num_free_bufs(struct qbman_bp_query_rslt *a) { return le32_to_cpu(a->fill); } + +/** + * qbman_swp_set_irq_coalescing() - Set new IRQ coalescing values + * @p: the software portal object + * @irq_threshold: interrupt threshold + * @irq_holdoff: interrupt holdoff (timeout) period in us + * + * Return 0 for success, or negative error code on error. + */ +int qbman_swp_set_irq_coalescing(struct qbman_swp *p, u32 irq_threshold, + u32 irq_holdoff) +{ + u32 itp, max_holdoff; + + /* Convert irq_holdoff value from usecs to 256 QBMAN clock cycles + * increments. This depends to the QBMAN internal frequency. + */ + itp = (irq_holdoff * 1000) / p->desc->qman_256_cycles_per_ns; + if (itp < 0 || itp > 4096) { + max_holdoff = (p->desc->qman_256_cycles_per_ns * 4096) / 1000; + pr_err("irq_holdoff must be between 0..%dus\n", max_holdoff); + return -EINVAL; + } + + if (irq_threshold >= p->dqrr.dqrr_size || irq_threshold < 0) { + pr_err("irq_threshold must be between 0..%d\n", + p->dqrr.dqrr_size - 1); + return -EINVAL; + } + + p->irq_threshold = irq_threshold; + p->irq_holdoff = irq_holdoff; + + qbman_write_register(p, QBMAN_CINH_SWP_DQRR_ITR, irq_threshold); + qbman_write_register(p, QBMAN_CINH_SWP_ITPR, itp); + + return 0; +} + +/** + * qbman_swp_get_irq_coalescing() - Get the current IRQ coalescing parameters + * @p: the software portal object + * @irq_threshold: interrupt threshold (an IRQ is generated when there are more + * DQRR entries in the portal than the threshold) + * @irq_holdoff: interrupt holdoff (timeout) period in us + */ +void qbman_swp_get_irq_coalescing(struct qbman_swp *p, u32 *irq_threshold, + u32 *irq_holdoff) +{ + if (irq_threshold) + *irq_threshold = p->irq_threshold; + if (irq_holdoff) + *irq_holdoff = p->irq_holdoff; +} diff --git a/drivers/soc/fsl/dpio/qbman-portal.h b/drivers/soc/fsl/dpio/qbman-portal.h index f058289416af..4ea2dd950a2a 100644 --- a/drivers/soc/fsl/dpio/qbman-portal.h +++ b/drivers/soc/fsl/dpio/qbman-portal.h @@ -25,6 +25,7 @@ struct qbman_swp_desc { void __iomem *cinh_bar; /* Cache-inhibited portal base address */ u32 qman_version; u32 qman_clk; + u32 qman_256_cycles_per_ns; }; #define QBMAN_SWP_INTERRUPT_EQRI 0x01 @@ -157,6 +158,10 @@ struct qbman_swp { } eqcr; spinlock_t access_spinlock; + + /* Interrupt coalescing */ + u32 irq_threshold; + u32 irq_holdoff; }; /* Function pointers */ @@ -649,4 +654,10 @@ static inline const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s) return qbman_swp_dqrr_next_ptr(s); } +int qbman_swp_set_irq_coalescing(struct qbman_swp *p, u32 irq_threshold, + u32 irq_holdoff); + +void qbman_swp_get_irq_coalescing(struct qbman_swp *p, u32 *irq_threshold, + u32 *irq_holdoff); + #endif /* __FSL_QBMAN_PORTAL_H */ diff --git a/include/soc/fsl/dpaa2-io.h b/include/soc/fsl/dpaa2-io.h index 45de23daefb7..31303ff32808 100644 --- a/include/soc/fsl/dpaa2-io.h +++ b/include/soc/fsl/dpaa2-io.h @@ -130,4 +130,8 @@ int dpaa2_io_query_fq_count(struct dpaa2_io *d, u32 fqid, u32 *fcnt, u32 *bcnt); int dpaa2_io_query_bp_count(struct dpaa2_io *d, u16 bpid, u32 *num); + +int dpaa2_io_set_irq_coalescing(struct dpaa2_io *d, u32 irq_holdoff); +void dpaa2_io_get_irq_coalescing(struct dpaa2_io *d, u32 *irq_holdoff); + #endif /* __FSL_DPAA2_IO_H */