From patchwork Wed Nov 10 08:39:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmlhbyBIdWFuZyAo6buE5b2qKQ==?= X-Patchwork-Id: 12611587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DDC4C4332F for ; Wed, 10 Nov 2021 08:40:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 83F94611F2 for ; Wed, 10 Nov 2021 08:40:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230420AbhKJInI (ORCPT ); Wed, 10 Nov 2021 03:43:08 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:47094 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230340AbhKJInD (ORCPT ); Wed, 10 Nov 2021 03:43:03 -0500 X-UUID: 83e6105f97fb40e0aee8d088f917e3ac-20211110 X-UUID: 83e6105f97fb40e0aee8d088f917e3ac-20211110 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1240269246; Wed, 10 Nov 2021 16:40:13 +0800 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 10 Nov 2021 16:40:11 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs10n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 10 Nov 2021 16:40:10 +0800 From: Biao Huang To: , Jakub Kicinski , Rob Herring CC: Matthias Brugger , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Biao Huang , , , , , , , , Subject: [PATCH 5/5] arm64: dts: mt8195: add ethernet device node Date: Wed, 10 Nov 2021 16:39:48 +0800 Message-ID: <20211110083948.6082-6-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110083948.6082-1-biao.huang@mediatek.com> References: <20211110083948.6082-1-biao.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch adds device node for mt8195 ethernet. Signed-off-by: Biao Huang --- arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 92 +++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 70 ++++++++++++++++ 2 files changed, 162 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts index 5cce9a5d3163..d90308f80229 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -5,6 +5,8 @@ */ /dts-v1/; #include "mt8195.dtsi" +#include +#include / { model = "MediaTek MT8195 evaluation board"; @@ -32,6 +34,96 @@ reserved_memory: reserved-memory { }; }; +ð { + phy-mode ="rgmii-rxid"; + phy-handle = <ð_phy0>; + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us = <0 10000 10000>; + mediatek,tx-delay-ps = <2030>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default>; + pinctrl-1 = <ð_sleep>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + eth_phy0: eth_phy0@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + }; + }; +}; + +&pio { + eth_default: eth_default { + txd_pins { + pinmux = , + , + , + ; + drive-strength = ; + }; + cc_pins { + pinmux = , + , + , + ; + drive-strength = ; + }; + rxd_pins { + pinmux = , + , + , + ; + }; + mdio_pins { + pinmux = , + ; + input-enable; + }; + power_pins { + pinmux = , + ; + output-high; + }; + }; + + eth_sleep: eth_sleep { + txd_pins { + pinmux = , + , + , + ; + }; + cc_pins { + pinmux = , + , + , + ; + }; + rxd_pins { + pinmux = , + , + , + ; + }; + mdio_pins { + pinmux = , + ; + input-disable; + bias-disable; + }; + power_pins { + pinmux = , + ; + input-disable; + bias-disable; + }; + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index a59c0e9d1fc2..f30a60dca5ef 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -823,6 +823,76 @@ spis1: spi@1101e000 { status = "disabled"; }; + eth: ethernet@11021000 { + compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; + reg = <0 0x11021000 0 0x4000>; + interrupts = ; + interrupt-names = "macirq"; + mac-address = [00 55 7b b5 7d f7]; + clock-names = "axi", + "apb", + "mac_cg", + "mac_main", + "ptp_ref", + "rmii_internal"; + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>, + <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, + <&topckgen CLK_TOP_ETHPLL_D8>, + <&topckgen CLK_TOP_ETHPLL_D10>; + power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; + mediatek,pericfg = <&infracfg_ao>; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + clk_csr = <0>; + status = "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,priority = <0x0>; + }; + }; + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <3>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + queue1 { + snps,weight = <0x11>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + queue2 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + }; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc"; reg = <0 0x11230000 0 0x10000>,