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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id i10sm9131821ejw.48.2021.12.07.07.00.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Dec 2021 07:00:01 -0800 (PST) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Ansuel Smith Subject: [net-next RFC PATCH 6/6] net: dsa: qca8k: cache lo and hi for mdio write Date: Tue, 7 Dec 2021 15:59:42 +0100 Message-Id: <20211207145942.7444-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211207145942.7444-1-ansuelsmth@gmail.com> References: <20211207145942.7444-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC From Documentation, we can cache lo and hi the same way we do with the page. This massively reduce the mdio write as 3/4 of the time we only require to write the lo or hi part for a mdio write. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 49 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 44 insertions(+), 5 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index d2c6139be9ac..64643f1e2f16 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -94,6 +94,48 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page) *page = regaddr & 0x3ff; } +static u16 qca8k_current_lo = 0xffff; + +static int +qca8k_set_lo(struct mii_bus *bus, int phy_id, u32 regnum, u16 lo) +{ + int ret; + + if (lo == qca8k_current_lo) { + // pr_info("SAME LOW"); + return 0; + } + + ret = bus->write(bus, phy_id, regnum, lo); + if (ret < 0) + dev_err_ratelimited(&bus->dev, + "failed to write qca8k 32bit lo register\n"); + + qca8k_current_lo = lo; + return 0; +} + +static u16 qca8k_current_hi = 0xffff; + +static int +qca8k_set_hi(struct mii_bus *bus, int phy_id, u32 regnum, u16 hi) +{ + int ret; + + if (hi == qca8k_current_hi) { + // pr_info("SAME HI"); + return 0; + } + + ret = bus->write(bus, phy_id, regnum, hi); + if (ret < 0) + dev_err_ratelimited(&bus->dev, + "failed to write qca8k 32bit hi register\n"); + + qca8k_current_hi = hi; + return 0; +} + static int qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val) { @@ -125,12 +167,9 @@ qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val) lo = val & 0xffff; hi = (u16)(val >> 16); - ret = bus->write(bus, phy_id, regnum, lo); + ret = qca8k_set_lo(bus, phy_id, regnum, lo); if (ret >= 0) - ret = bus->write(bus, phy_id, regnum + 1, hi); - if (ret < 0) - dev_err_ratelimited(&bus->dev, - "failed to write qca8k 32bit register\n"); + ret = qca8k_set_hi(bus, phy_id, regnum + 1, hi); } static int