From patchwork Thu Dec 16 20:13:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luiz Angelo Daros de Luca X-Patchwork-Id: 12682451 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12C6FC433EF for ; Thu, 16 Dec 2021 20:14:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241250AbhLPUOg (ORCPT ); Thu, 16 Dec 2021 15:14:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241244AbhLPUOf (ORCPT ); Thu, 16 Dec 2021 15:14:35 -0500 Received: from mail-qt1-x82e.google.com (mail-qt1-x82e.google.com [IPv6:2607:f8b0:4864:20::82e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD0CBC061574 for ; Thu, 16 Dec 2021 12:14:34 -0800 (PST) Received: by mail-qt1-x82e.google.com with SMTP id j17so454221qtx.2 for ; Thu, 16 Dec 2021 12:14:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ExjjKO3DOVJ4Cp9V/RQVwG+nld3rr/GkJJrIzBSNsN0=; b=dRWX0Si6nP6Irb+fbzQg5eYpc/1zZxtr19bjcfXMyDKcGsaxWv78IrlNIgVI2K3Rvg 6eVwSvnhdAPLsFFVhFT9eC40WKyIzT/BKFKWyZvrgA9Hm8uG838IqXsFdVmzDES68usn XKl7q36vsw8tiH/hr9kHeh/eTzEz9JUOgzKZ1hslL56lNlgXG00+/ByUBoeed1MZEtad tMcns5A4vGSd8FTAFhKjkE/dAMk86ibIdXhMpF1JnD0JaXOaBx5CQnSLOHeXXoweqUDZ 7PGUlgTL5HNpOY4807Znnt889+uaDmQwxOPRSgTYLXPjHf8qqv/byTiNwRQl0fvrKpb6 HuzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ExjjKO3DOVJ4Cp9V/RQVwG+nld3rr/GkJJrIzBSNsN0=; b=FqnBGf997RiHXNHLyanuVHWsXshZuZJAYN0gXq+aR+zTwa1hgwu8G0WFEvczdfnS2e u0H5prsuaf80suRpYgXhpkvg07vSRqYufCfLCirYk754/BPIy9skBirQ8D+VfbBgkjwC ckSNgh5Ho2C4mHgQ6hVsjFchpu30LBU2BGVPkkaYV6DK9IDz9xqYQ8XFpZZZvmzuahyZ dHBhQQAfwmcMrfIbCDPgOhw7zmbihqflQAyT7xKwdwCrH72UkjVGdV+Q+QuuNIAQinKK MQpO4Nq5hFFNTyz2ZJcGC9+U2QdpF4S29I7muC7wxyI0Zrrq5wMd/IluaWhXZqmM+SSG fqaw== X-Gm-Message-State: AOAM530mGsmAT1lwnAEnARig8uxI3Y1Vi0ExH9tKt2RMAmr/HeDFuh5y wwS855qURyBETMlq1ckAEVzApT0o5oLxcQ== X-Google-Smtp-Source: ABdhPJylgKV5rFl70J4zImbrPBCzW9jCJfdF7FEiAFXrHSR3EFYt0jKnX4+XHk1WuIblky84DBgolg== X-Received: by 2002:ac8:5c54:: with SMTP id j20mr18582512qtj.121.1639685672480; Thu, 16 Dec 2021 12:14:32 -0800 (PST) Received: from tresc043793.tre-sc.gov.br (187-049-235-234.floripa.net.br. [187.49.235.234]) by smtp.gmail.com with ESMTPSA id a15sm5110266qtb.5.2021.12.16.12.14.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 12:14:31 -0800 (PST) From: luizluca@gmail.com To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 07/13] net: dsa: rtl8365mb: rename rtl8365mb to rtl8367c Date: Thu, 16 Dec 2021 17:13:36 -0300 Message-Id: <20211216201342.25587-8-luizluca@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211216201342.25587-1-luizluca@gmail.com> References: <20211216201342.25587-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Luiz Angelo Daros de Luca rtl8365mb refers to a single device supported by the driver. The rtl8367c does not refer to any real device, but it is the driver version name used by Realtek. Tested-by: Arınç ÜNAL Signed-off-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/Kconfig | 9 +- drivers/net/dsa/realtek/Makefile | 2 +- drivers/net/dsa/realtek/realtek-smi.c | 4 +- drivers/net/dsa/realtek/realtek.h | 2 +- drivers/net/dsa/realtek/rtl8367c.c | 1321 ++++++++++++------------- drivers/net/phy/realtek.c | 2 +- 6 files changed, 666 insertions(+), 674 deletions(-) diff --git a/drivers/net/dsa/realtek/Kconfig b/drivers/net/dsa/realtek/Kconfig index c002a84a00f5..874574db9177 100644 --- a/drivers/net/dsa/realtek/Kconfig +++ b/drivers/net/dsa/realtek/Kconfig @@ -16,14 +16,17 @@ config NET_DSA_REALTEK_SMI help Select to enable support for registering switches connected through SMI. -config NET_DSA_REALTEK_RTL8365MB - tristate "Realtek RTL8365MB switch subdriver" +config NET_DSA_REALTEK_RTL8367C + tristate "Realtek RTL8367C switch subdriver" default y depends on NET_DSA_REALTEK depends on NET_DSA_REALTEK_SMI select NET_DSA_TAG_RTL8_4 help - Select to enable support for Realtek RTL8365MB + Select to enable support for Realtek RTL8365MB-VC. This subdriver + might also support RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB, RTL8364NB, + RTL8364NB-VB, RTL8366SC, RTL8367RB-VB, RTL8367S, RTL8367SB, RTL8370MB, RTL8310SR + in the future. config NET_DSA_REALTEK_RTL8366RB tristate "Realtek RTL8366RB switch subdriver" diff --git a/drivers/net/dsa/realtek/Makefile b/drivers/net/dsa/realtek/Makefile index efb9568077f5..84d5ab062c89 100644 --- a/drivers/net/dsa/realtek/Makefile +++ b/drivers/net/dsa/realtek/Makefile @@ -2,4 +2,4 @@ obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o obj-$(CONFIG_NET_DSA_REALTEK_RTL8366RB) += rtl8366.o rtl8366-objs := rtl8366-core.o rtl8366rb.o -obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) += rtl8367c.o +obj-$(CONFIG_NET_DSA_REALTEK_RTL8367C) += rtl8367c.o diff --git a/drivers/net/dsa/realtek/realtek-smi.c b/drivers/net/dsa/realtek/realtek-smi.c index f10acd7d3636..258f90956cec 100644 --- a/drivers/net/dsa/realtek/realtek-smi.c +++ b/drivers/net/dsa/realtek/realtek-smi.c @@ -506,10 +506,10 @@ static const struct of_device_id realtek_smi_of_match[] = { .compatible = "realtek,rtl8366s", .data = NULL, }, -#if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8365MB) +#if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8367C) { .compatible = "realtek,rtl8365mb", - .data = &rtl8365mb_variant, + .data = &rtl8367c_variant, }, #endif { /* sentinel */ }, diff --git a/drivers/net/dsa/realtek/realtek.h b/drivers/net/dsa/realtek/realtek.h index daca0c0b7ea2..976cb7823c92 100644 --- a/drivers/net/dsa/realtek/realtek.h +++ b/drivers/net/dsa/realtek/realtek.h @@ -134,6 +134,6 @@ int rtl8366_get_sset_count(struct dsa_switch *ds, int port, int sset); void rtl8366_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data); extern const struct realtek_variant rtl8366rb_variant; -extern const struct realtek_variant rtl8365mb_variant; +extern const struct realtek_variant rtl8367c_variant; #endif /* _REALTEK_SMI_H */ diff --git a/drivers/net/dsa/realtek/rtl8367c.c b/drivers/net/dsa/realtek/rtl8367c.c index 488b17a68226..98ec793a82bc 100644 --- a/drivers/net/dsa/realtek/rtl8367c.c +++ b/drivers/net/dsa/realtek/rtl8367c.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -/* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch. +/* Realtek SMI subdriver for the Realtek RTL8367C ethernet switches. * * Copyright (C) 2021 Alvin Šipraga * Copyright (C) 2021 Michael Rasmussen @@ -52,19 +52,7 @@ * the driver will manually reprogram some registers using jam tables to reach * an initial state defined by the vendor driver. * - * This Linux driver is written based on an OS-agnostic vendor driver from - * Realtek. The reference GPL-licensed sources can be found in the OpenWrt - * source tree under the name rtl8367c. The vendor driver claims to support a - * number of similar switch controllers from Realtek, but the only hardware we - * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under - * the name RTL8367C. Although one wishes that the 'C' stood for some kind of - * common hardware revision, there exist examples of chips with the suffix -VC - * which are explicitly not supported by the rtl8367c driver and which instead - * require the rtl8367d vendor driver. With all this uncertainty, the driver has - * been modestly named rtl8365mb. Future implementors may wish to rename things - * accordingly. - * - * In the same family of chips, some carry up to 8 user ports and up to 2 + * In this family of chips, some carry up to 8 user ports and up to 2 * extension ports. Where possible this driver tries to make things generic, but * more work must be done to support these configurations. According to * documentation from Realtek, the family should include the following chips: @@ -102,202 +90,203 @@ #include "realtek.h" /* Chip-specific data and limits */ -#define RTL8365MB_CHIP_ID_8365MB_VC 0x6367 -#define RTL8365MB_CPU_PORT_NUM_8365MB_VC 6 -#define RTL8365MB_LEARN_LIMIT_MAX_8365MB_VC 2112 +#define RTL8367C_CHIP_ID_8365MB_VC 0x6367 +#define RTL8367C_CPU_PORT_NUM_8365MB_VC 6 + +#define RTL8367C_LEARN_LIMIT_MAX 2112 /* Family-specific data and limits */ -#define RTL8365MB_PHYADDRMAX 7 -#define RTL8365MB_NUM_PHYREGS 32 -#define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1) -#define RTL8365MB_MAX_NUM_PORTS (RTL8365MB_CPU_PORT_NUM_8365MB_VC + 1) +#define RTL8367C_PHYADDRMAX 7 +#define RTL8367C_NUM_PHYREGS 32 +#define RTL8367C_PHYREGMAX (RTL8367C_NUM_PHYREGS - 1) +#define RTL8367C_MAX_NUM_PORTS (RTL8367C_CPU_PORT_NUM_8365MB_VC + 1) /* Chip identification registers */ -#define RTL8365MB_CHIP_ID_REG 0x1300 +#define RTL8367C_CHIP_ID_REG 0x1300 -#define RTL8365MB_CHIP_VER_REG 0x1301 +#define RTL8367C_CHIP_VER_REG 0x1301 -#define RTL8365MB_MAGIC_REG 0x13C2 -#define RTL8365MB_MAGIC_VALUE 0x0249 +#define RTL8367C_MAGIC_REG 0x13C2 +#define RTL8367C_MAGIC_VALUE 0x0249 /* Chip reset register */ -#define RTL8365MB_CHIP_RESET_REG 0x1322 -#define RTL8365MB_CHIP_RESET_SW_MASK 0x0002 -#define RTL8365MB_CHIP_RESET_HW_MASK 0x0001 +#define RTL8367C_CHIP_RESET_REG 0x1322 +#define RTL8367C_CHIP_RESET_SW_MASK 0x0002 +#define RTL8367C_CHIP_RESET_HW_MASK 0x0001 /* Interrupt polarity register */ -#define RTL8365MB_INTR_POLARITY_REG 0x1100 -#define RTL8365MB_INTR_POLARITY_MASK 0x0001 -#define RTL8365MB_INTR_POLARITY_HIGH 0 -#define RTL8365MB_INTR_POLARITY_LOW 1 +#define RTL8367C_INTR_POLARITY_REG 0x1100 +#define RTL8367C_INTR_POLARITY_MASK 0x0001 +#define RTL8367C_INTR_POLARITY_HIGH 0 +#define RTL8367C_INTR_POLARITY_LOW 1 /* Interrupt control/status register - enable/check specific interrupt types */ -#define RTL8365MB_INTR_CTRL_REG 0x1101 -#define RTL8365MB_INTR_STATUS_REG 0x1102 -#define RTL8365MB_INTR_SLIENT_START_2_MASK 0x1000 -#define RTL8365MB_INTR_SLIENT_START_MASK 0x0800 -#define RTL8365MB_INTR_ACL_ACTION_MASK 0x0200 -#define RTL8365MB_INTR_CABLE_DIAG_FIN_MASK 0x0100 -#define RTL8365MB_INTR_INTERRUPT_8051_MASK 0x0080 -#define RTL8365MB_INTR_LOOP_DETECTION_MASK 0x0040 -#define RTL8365MB_INTR_GREEN_TIMER_MASK 0x0020 -#define RTL8365MB_INTR_SPECIAL_CONGEST_MASK 0x0010 -#define RTL8365MB_INTR_SPEED_CHANGE_MASK 0x0008 -#define RTL8365MB_INTR_LEARN_OVER_MASK 0x0004 -#define RTL8365MB_INTR_METER_EXCEEDED_MASK 0x0002 -#define RTL8365MB_INTR_LINK_CHANGE_MASK 0x0001 -#define RTL8365MB_INTR_ALL_MASK \ - (RTL8365MB_INTR_SLIENT_START_2_MASK | \ - RTL8365MB_INTR_SLIENT_START_MASK | \ - RTL8365MB_INTR_ACL_ACTION_MASK | \ - RTL8365MB_INTR_CABLE_DIAG_FIN_MASK | \ - RTL8365MB_INTR_INTERRUPT_8051_MASK | \ - RTL8365MB_INTR_LOOP_DETECTION_MASK | \ - RTL8365MB_INTR_GREEN_TIMER_MASK | \ - RTL8365MB_INTR_SPECIAL_CONGEST_MASK | \ - RTL8365MB_INTR_SPEED_CHANGE_MASK | \ - RTL8365MB_INTR_LEARN_OVER_MASK | \ - RTL8365MB_INTR_METER_EXCEEDED_MASK | \ - RTL8365MB_INTR_LINK_CHANGE_MASK) +#define RTL8367C_INTR_CTRL_REG 0x1101 +#define RTL8367C_INTR_STATUS_REG 0x1102 +#define RTL8367C_INTR_SLIENT_START_2_MASK 0x1000 +#define RTL8367C_INTR_SLIENT_START_MASK 0x0800 +#define RTL8367C_INTR_ACL_ACTION_MASK 0x0200 +#define RTL8367C_INTR_CABLE_DIAG_FIN_MASK 0x0100 +#define RTL8367C_INTR_INTERRUPT_8051_MASK 0x0080 +#define RTL8367C_INTR_LOOP_DETECTION_MASK 0x0040 +#define RTL8367C_INTR_GREEN_TIMER_MASK 0x0020 +#define RTL8367C_INTR_SPECIAL_CONGEST_MASK 0x0010 +#define RTL8367C_INTR_SPEED_CHANGE_MASK 0x0008 +#define RTL8367C_INTR_LEARN_OVER_MASK 0x0004 +#define RTL8367C_INTR_METER_EXCEEDED_MASK 0x0002 +#define RTL8367C_INTR_LINK_CHANGE_MASK 0x0001 +#define RTL8367C_INTR_ALL_MASK \ + (RTL8367C_INTR_SLIENT_START_2_MASK | \ + RTL8367C_INTR_SLIENT_START_MASK | \ + RTL8367C_INTR_ACL_ACTION_MASK | \ + RTL8367C_INTR_CABLE_DIAG_FIN_MASK | \ + RTL8367C_INTR_INTERRUPT_8051_MASK | \ + RTL8367C_INTR_LOOP_DETECTION_MASK | \ + RTL8367C_INTR_GREEN_TIMER_MASK | \ + RTL8367C_INTR_SPECIAL_CONGEST_MASK | \ + RTL8367C_INTR_SPEED_CHANGE_MASK | \ + RTL8367C_INTR_LEARN_OVER_MASK | \ + RTL8367C_INTR_METER_EXCEEDED_MASK | \ + RTL8367C_INTR_LINK_CHANGE_MASK) /* Per-port interrupt type status registers */ -#define RTL8365MB_PORT_LINKDOWN_IND_REG 0x1106 -#define RTL8365MB_PORT_LINKDOWN_IND_MASK 0x07FF +#define RTL8367C_PORT_LINKDOWN_IND_REG 0x1106 +#define RTL8367C_PORT_LINKDOWN_IND_MASK 0x07FF -#define RTL8365MB_PORT_LINKUP_IND_REG 0x1107 -#define RTL8365MB_PORT_LINKUP_IND_MASK 0x07FF +#define RTL8367C_PORT_LINKUP_IND_REG 0x1107 +#define RTL8367C_PORT_LINKUP_IND_MASK 0x07FF /* PHY indirect access registers */ -#define RTL8365MB_INDIRECT_ACCESS_CTRL_REG 0x1F00 -#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK 0x0002 -#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ 0 -#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE 1 -#define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK 0x0001 -#define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE 1 -#define RTL8365MB_INDIRECT_ACCESS_STATUS_REG 0x1F01 -#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG 0x1F02 -#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0) -#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5) -#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8) -#define RTL8365MB_PHY_BASE 0x2000 -#define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03 -#define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG 0x1F04 +#define RTL8367C_INDIRECT_ACCESS_CTRL_REG 0x1F00 +#define RTL8367C_INDIRECT_ACCESS_CTRL_RW_MASK 0x0002 +#define RTL8367C_INDIRECT_ACCESS_CTRL_RW_READ 0 +#define RTL8367C_INDIRECT_ACCESS_CTRL_RW_WRITE 1 +#define RTL8367C_INDIRECT_ACCESS_CTRL_CMD_MASK 0x0001 +#define RTL8367C_INDIRECT_ACCESS_CTRL_CMD_VALUE 1 +#define RTL8367C_INDIRECT_ACCESS_STATUS_REG 0x1F01 +#define RTL8367C_INDIRECT_ACCESS_ADDRESS_REG 0x1F02 +#define RTL8367C_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0) +#define RTL8367C_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5) +#define RTL8367C_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8) +#define RTL8367C_PHY_BASE 0x2000 +#define RTL8367C_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03 +#define RTL8367C_INDIRECT_ACCESS_READ_DATA_REG 0x1F04 /* PHY OCP address prefix register */ -#define RTL8365MB_GPHY_OCP_MSB_0_REG 0x1D15 -#define RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0 -#define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK 0xFC00 +#define RTL8367C_GPHY_OCP_MSB_0_REG 0x1D15 +#define RTL8367C_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0 +#define RTL8367C_PHY_OCP_ADDR_PREFIX_MASK 0xFC00 /* The PHY OCP addresses of PHY registers 0~31 start here */ -#define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400 +#define RTL8367C_PHY_OCP_ADDR_PHYREG_BASE 0xA400 /* EXT port interface mode values - used in DIGITAL_INTERFACE_SELECT */ -#define RTL8365MB_EXT_PORT_MODE_DISABLE 0 -#define RTL8365MB_EXT_PORT_MODE_RGMII 1 -#define RTL8365MB_EXT_PORT_MODE_MII_MAC 2 -#define RTL8365MB_EXT_PORT_MODE_MII_PHY 3 -#define RTL8365MB_EXT_PORT_MODE_TMII_MAC 4 -#define RTL8365MB_EXT_PORT_MODE_TMII_PHY 5 -#define RTL8365MB_EXT_PORT_MODE_GMII 6 -#define RTL8365MB_EXT_PORT_MODE_RMII_MAC 7 -#define RTL8365MB_EXT_PORT_MODE_RMII_PHY 8 -#define RTL8365MB_EXT_PORT_MODE_SGMII 9 -#define RTL8365MB_EXT_PORT_MODE_HSGMII 10 -#define RTL8365MB_EXT_PORT_MODE_1000X_100FX 11 -#define RTL8365MB_EXT_PORT_MODE_1000X 12 -#define RTL8365MB_EXT_PORT_MODE_100FX 13 +#define RTL8367C_EXT_PORT_MODE_DISABLE 0 +#define RTL8367C_EXT_PORT_MODE_RGMII 1 +#define RTL8367C_EXT_PORT_MODE_MII_MAC 2 +#define RTL8367C_EXT_PORT_MODE_MII_PHY 3 +#define RTL8367C_EXT_PORT_MODE_TMII_MAC 4 +#define RTL8367C_EXT_PORT_MODE_TMII_PHY 5 +#define RTL8367C_EXT_PORT_MODE_GMII 6 +#define RTL8367C_EXT_PORT_MODE_RMII_MAC 7 +#define RTL8367C_EXT_PORT_MODE_RMII_PHY 8 +#define RTL8367C_EXT_PORT_MODE_SGMII 9 +#define RTL8367C_EXT_PORT_MODE_HSGMII 10 +#define RTL8367C_EXT_PORT_MODE_1000X_100FX 11 +#define RTL8367C_EXT_PORT_MODE_1000X 12 +#define RTL8367C_EXT_PORT_MODE_100FX 13 /* EXT port interface mode configuration registers 0~1 */ -#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 0x1305 -#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 -#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extport) \ - (RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 + \ +#define RTL8367C_DIGITAL_INTERFACE_SELECT_REG0 0x1305 +#define RTL8367C_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 +#define RTL8367C_DIGITAL_INTERFACE_SELECT_REG(_extport) \ + (RTL8367C_DIGITAL_INTERFACE_SELECT_REG0 + \ ((_extport) >> 1) * (0x13C3 - 0x1305)) -#define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extport) \ +#define RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extport) \ (0xF << (((_extport) % 2))) -#define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extport) \ +#define RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extport) \ (((_extport) % 2) * 4) /* EXT port RGMII TX/RX delay configuration registers 1~2 */ -#define RTL8365MB_EXT_RGMXF_REG1 0x1307 -#define RTL8365MB_EXT_RGMXF_REG2 0x13C5 -#define RTL8365MB_EXT_RGMXF_REG(_extport) \ - (RTL8365MB_EXT_RGMXF_REG1 + \ +#define RTL8367C_EXT_RGMXF_REG1 0x1307 +#define RTL8367C_EXT_RGMXF_REG2 0x13C5 +#define RTL8367C_EXT_RGMXF_REG(_extport) \ + (RTL8367C_EXT_RGMXF_REG1 + \ (((_extport) >> 1) * (0x13C5 - 0x1307))) -#define RTL8365MB_EXT_RGMXF_RXDELAY_MASK 0x0007 -#define RTL8365MB_EXT_RGMXF_TXDELAY_MASK 0x0008 +#define RTL8367C_EXT_RGMXF_RXDELAY_MASK 0x0007 +#define RTL8367C_EXT_RGMXF_TXDELAY_MASK 0x0008 /* External port speed values - used in DIGITAL_INTERFACE_FORCE */ -#define RTL8365MB_PORT_SPEED_10M 0 -#define RTL8365MB_PORT_SPEED_100M 1 -#define RTL8365MB_PORT_SPEED_1000M 2 +#define RTL8367C_PORT_SPEED_10M 0 +#define RTL8367C_PORT_SPEED_100M 1 +#define RTL8367C_PORT_SPEED_1000M 2 /* EXT port force configuration registers 0~2 */ -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 0x1311 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extport) \ - (RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 + \ +#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG0 0x1310 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG1 0x1311 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_REG(_extport) \ + (RTL8367C_DIGITAL_INTERFACE_FORCE_REG0 + \ ((_extport) & 0x1) + \ ((((_extport) >> 1) & 0x1) * (0x13C4 - 0x1310))) -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0x0020 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK 0x0010 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0x0004 -#define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0x0003 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0x0020 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_LINK_MASK 0x0010 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0x0004 +#define RTL8367C_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0x0003 /* CPU port mask register - controls which ports are treated as CPU ports */ -#define RTL8365MB_CPU_PORT_MASK_REG 0x1219 -#define RTL8365MB_CPU_PORT_MASK_MASK 0x07FF +#define RTL8367C_CPU_PORT_MASK_REG 0x1219 +#define RTL8367C_CPU_PORT_MASK_MASK 0x07FF /* CPU control register */ -#define RTL8365MB_CPU_CTRL_REG 0x121A -#define RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400 -#define RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK 0x0200 -#define RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK 0x0080 -#define RTL8365MB_CPU_CTRL_TAG_POSITION_MASK 0x0040 -#define RTL8365MB_CPU_CTRL_TRAP_PORT_MASK 0x0038 -#define RTL8365MB_CPU_CTRL_INSERTMODE_MASK 0x0006 -#define RTL8365MB_CPU_CTRL_EN_MASK 0x0001 +#define RTL8367C_CPU_CTRL_REG 0x121A +#define RTL8367C_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400 +#define RTL8367C_CPU_CTRL_TAG_FORMAT_MASK 0x0200 +#define RTL8367C_CPU_CTRL_RXBYTECOUNT_MASK 0x0080 +#define RTL8367C_CPU_CTRL_TAG_POSITION_MASK 0x0040 +#define RTL8367C_CPU_CTRL_TRAP_PORT_MASK 0x0038 +#define RTL8367C_CPU_CTRL_INSERTMODE_MASK 0x0006 +#define RTL8367C_CPU_CTRL_EN_MASK 0x0001 /* Maximum packet length register */ -#define RTL8365MB_CFG0_MAX_LEN_REG 0x088C -#define RTL8365MB_CFG0_MAX_LEN_MASK 0x3FFF +#define RTL8367C_CFG0_MAX_LEN_REG 0x088C +#define RTL8367C_CFG0_MAX_LEN_MASK 0x3FFF /* Port learning limit registers */ -#define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE 0x0A20 -#define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \ - (RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport)) +#define RTL8367C_LUT_PORT_LEARN_LIMIT_BASE 0x0A20 +#define RTL8367C_LUT_PORT_LEARN_LIMIT_REG(_physport) \ + (RTL8367C_LUT_PORT_LEARN_LIMIT_BASE + (_physport)) /* Port isolation (forwarding mask) registers */ -#define RTL8365MB_PORT_ISOLATION_REG_BASE 0x08A2 -#define RTL8365MB_PORT_ISOLATION_REG(_physport) \ - (RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport)) -#define RTL8365MB_PORT_ISOLATION_MASK 0x07FF +#define RTL8367C_PORT_ISOLATION_REG_BASE 0x08A2 +#define RTL8367C_PORT_ISOLATION_REG(_physport) \ + (RTL8367C_PORT_ISOLATION_REG_BASE + (_physport)) +#define RTL8367C_PORT_ISOLATION_MASK 0x07FF /* MSTP port state registers - indexed by tree instance */ -#define RTL8365MB_MSTI_CTRL_BASE 0x0A00 -#define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \ - (RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3)) -#define RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1) -#define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \ - (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport))) +#define RTL8367C_MSTI_CTRL_BASE 0x0A00 +#define RTL8367C_MSTI_CTRL_REG(_msti, _physport) \ + (RTL8367C_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3)) +#define RTL8367C_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1) +#define RTL8367C_MSTI_CTRL_PORT_STATE_MASK(_physport) \ + (0x3 << RTL8367C_MSTI_CTRL_PORT_STATE_OFFSET((_physport))) /* MIB counter value registers */ -#define RTL8365MB_MIB_COUNTER_BASE 0x1000 -#define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x)) +#define RTL8367C_MIB_COUNTER_BASE 0x1000 +#define RTL8367C_MIB_COUNTER_REG(_x) (RTL8367C_MIB_COUNTER_BASE + (_x)) /* MIB counter address register */ -#define RTL8365MB_MIB_ADDRESS_REG 0x1004 -#define RTL8365MB_MIB_ADDRESS_PORT_OFFSET 0x007C -#define RTL8365MB_MIB_ADDRESS(_p, _x) \ - (((RTL8365MB_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2) +#define RTL8367C_MIB_ADDRESS_REG 0x1004 +#define RTL8367C_MIB_ADDRESS_PORT_OFFSET 0x007C +#define RTL8367C_MIB_ADDRESS(_p, _x) \ + (((RTL8367C_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2) -#define RTL8365MB_MIB_CTRL0_REG 0x1005 -#define RTL8365MB_MIB_CTRL0_RESET_MASK 0x0002 -#define RTL8365MB_MIB_CTRL0_BUSY_MASK 0x0001 +#define RTL8367C_MIB_CTRL0_REG 0x1005 +#define RTL8367C_MIB_CTRL0_RESET_MASK 0x0002 +#define RTL8367C_MIB_CTRL0_BUSY_MASK 0x0001 /* The DSA callback .get_stats64 runs in atomic context, so we are not allowed * to block. On the other hand, accessing MIB counters absolutely requires us to @@ -305,149 +294,149 @@ * asynchronously and updates some private data, which the callback can then * fetch atomically. Three seconds should be a good enough polling interval. */ -#define RTL8365MB_STATS_INTERVAL_JIFFIES (3 * HZ) - -enum rtl8365mb_mib_counter_index { - RTL8365MB_MIB_ifInOctets, - RTL8365MB_MIB_dot3StatsFCSErrors, - RTL8365MB_MIB_dot3StatsSymbolErrors, - RTL8365MB_MIB_dot3InPauseFrames, - RTL8365MB_MIB_dot3ControlInUnknownOpcodes, - RTL8365MB_MIB_etherStatsFragments, - RTL8365MB_MIB_etherStatsJabbers, - RTL8365MB_MIB_ifInUcastPkts, - RTL8365MB_MIB_etherStatsDropEvents, - RTL8365MB_MIB_ifInMulticastPkts, - RTL8365MB_MIB_ifInBroadcastPkts, - RTL8365MB_MIB_inMldChecksumError, - RTL8365MB_MIB_inIgmpChecksumError, - RTL8365MB_MIB_inMldSpecificQuery, - RTL8365MB_MIB_inMldGeneralQuery, - RTL8365MB_MIB_inIgmpSpecificQuery, - RTL8365MB_MIB_inIgmpGeneralQuery, - RTL8365MB_MIB_inMldLeaves, - RTL8365MB_MIB_inIgmpLeaves, - RTL8365MB_MIB_etherStatsOctets, - RTL8365MB_MIB_etherStatsUnderSizePkts, - RTL8365MB_MIB_etherOversizeStats, - RTL8365MB_MIB_etherStatsPkts64Octets, - RTL8365MB_MIB_etherStatsPkts65to127Octets, - RTL8365MB_MIB_etherStatsPkts128to255Octets, - RTL8365MB_MIB_etherStatsPkts256to511Octets, - RTL8365MB_MIB_etherStatsPkts512to1023Octets, - RTL8365MB_MIB_etherStatsPkts1024to1518Octets, - RTL8365MB_MIB_ifOutOctets, - RTL8365MB_MIB_dot3StatsSingleCollisionFrames, - RTL8365MB_MIB_dot3StatsMultipleCollisionFrames, - RTL8365MB_MIB_dot3StatsDeferredTransmissions, - RTL8365MB_MIB_dot3StatsLateCollisions, - RTL8365MB_MIB_etherStatsCollisions, - RTL8365MB_MIB_dot3StatsExcessiveCollisions, - RTL8365MB_MIB_dot3OutPauseFrames, - RTL8365MB_MIB_ifOutDiscards, - RTL8365MB_MIB_dot1dTpPortInDiscards, - RTL8365MB_MIB_ifOutUcastPkts, - RTL8365MB_MIB_ifOutMulticastPkts, - RTL8365MB_MIB_ifOutBroadcastPkts, - RTL8365MB_MIB_outOampduPkts, - RTL8365MB_MIB_inOampduPkts, - RTL8365MB_MIB_inIgmpJoinsSuccess, - RTL8365MB_MIB_inIgmpJoinsFail, - RTL8365MB_MIB_inMldJoinsSuccess, - RTL8365MB_MIB_inMldJoinsFail, - RTL8365MB_MIB_inReportSuppressionDrop, - RTL8365MB_MIB_inLeaveSuppressionDrop, - RTL8365MB_MIB_outIgmpReports, - RTL8365MB_MIB_outIgmpLeaves, - RTL8365MB_MIB_outIgmpGeneralQuery, - RTL8365MB_MIB_outIgmpSpecificQuery, - RTL8365MB_MIB_outMldReports, - RTL8365MB_MIB_outMldLeaves, - RTL8365MB_MIB_outMldGeneralQuery, - RTL8365MB_MIB_outMldSpecificQuery, - RTL8365MB_MIB_inKnownMulticastPkts, - RTL8365MB_MIB_END, +#define RTL8367C_STATS_INTERVAL_JIFFIES (3 * HZ) + +enum rtl8367c_mib_counter_index { + RTL8367C_MIB_ifInOctets, + RTL8367C_MIB_dot3StatsFCSErrors, + RTL8367C_MIB_dot3StatsSymbolErrors, + RTL8367C_MIB_dot3InPauseFrames, + RTL8367C_MIB_dot3ControlInUnknownOpcodes, + RTL8367C_MIB_etherStatsFragments, + RTL8367C_MIB_etherStatsJabbers, + RTL8367C_MIB_ifInUcastPkts, + RTL8367C_MIB_etherStatsDropEvents, + RTL8367C_MIB_ifInMulticastPkts, + RTL8367C_MIB_ifInBroadcastPkts, + RTL8367C_MIB_inMldChecksumError, + RTL8367C_MIB_inIgmpChecksumError, + RTL8367C_MIB_inMldSpecificQuery, + RTL8367C_MIB_inMldGeneralQuery, + RTL8367C_MIB_inIgmpSpecificQuery, + RTL8367C_MIB_inIgmpGeneralQuery, + RTL8367C_MIB_inMldLeaves, + RTL8367C_MIB_inIgmpLeaves, + RTL8367C_MIB_etherStatsOctets, + RTL8367C_MIB_etherStatsUnderSizePkts, + RTL8367C_MIB_etherOversizeStats, + RTL8367C_MIB_etherStatsPkts64Octets, + RTL8367C_MIB_etherStatsPkts65to127Octets, + RTL8367C_MIB_etherStatsPkts128to255Octets, + RTL8367C_MIB_etherStatsPkts256to511Octets, + RTL8367C_MIB_etherStatsPkts512to1023Octets, + RTL8367C_MIB_etherStatsPkts1024to1518Octets, + RTL8367C_MIB_ifOutOctets, + RTL8367C_MIB_dot3StatsSingleCollisionFrames, + RTL8367C_MIB_dot3StatsMultipleCollisionFrames, + RTL8367C_MIB_dot3StatsDeferredTransmissions, + RTL8367C_MIB_dot3StatsLateCollisions, + RTL8367C_MIB_etherStatsCollisions, + RTL8367C_MIB_dot3StatsExcessiveCollisions, + RTL8367C_MIB_dot3OutPauseFrames, + RTL8367C_MIB_ifOutDiscards, + RTL8367C_MIB_dot1dTpPortInDiscards, + RTL8367C_MIB_ifOutUcastPkts, + RTL8367C_MIB_ifOutMulticastPkts, + RTL8367C_MIB_ifOutBroadcastPkts, + RTL8367C_MIB_outOampduPkts, + RTL8367C_MIB_inOampduPkts, + RTL8367C_MIB_inIgmpJoinsSuccess, + RTL8367C_MIB_inIgmpJoinsFail, + RTL8367C_MIB_inMldJoinsSuccess, + RTL8367C_MIB_inMldJoinsFail, + RTL8367C_MIB_inReportSuppressionDrop, + RTL8367C_MIB_inLeaveSuppressionDrop, + RTL8367C_MIB_outIgmpReports, + RTL8367C_MIB_outIgmpLeaves, + RTL8367C_MIB_outIgmpGeneralQuery, + RTL8367C_MIB_outIgmpSpecificQuery, + RTL8367C_MIB_outMldReports, + RTL8367C_MIB_outMldLeaves, + RTL8367C_MIB_outMldGeneralQuery, + RTL8367C_MIB_outMldSpecificQuery, + RTL8367C_MIB_inKnownMulticastPkts, + RTL8367C_MIB_END, }; -struct rtl8365mb_mib_counter { +struct rtl8367c_mib_counter { u32 offset; u32 length; const char *name; }; -#define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \ - [RTL8365MB_MIB_ ## _name] = { _offset, _length, #_name } - -static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = { - RTL8365MB_MAKE_MIB_COUNTER(0, 4, ifInOctets), - RTL8365MB_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors), - RTL8365MB_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors), - RTL8365MB_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames), - RTL8365MB_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes), - RTL8365MB_MAKE_MIB_COUNTER(12, 2, etherStatsFragments), - RTL8365MB_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers), - RTL8365MB_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts), - RTL8365MB_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents), - RTL8365MB_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts), - RTL8365MB_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts), - RTL8365MB_MAKE_MIB_COUNTER(24, 2, inMldChecksumError), - RTL8365MB_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError), - RTL8365MB_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery), - RTL8365MB_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery), - RTL8365MB_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery), - RTL8365MB_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery), - RTL8365MB_MAKE_MIB_COUNTER(36, 2, inMldLeaves), - RTL8365MB_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves), - RTL8365MB_MAKE_MIB_COUNTER(40, 4, etherStatsOctets), - RTL8365MB_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts), - RTL8365MB_MAKE_MIB_COUNTER(46, 2, etherOversizeStats), - RTL8365MB_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets), - RTL8365MB_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets), - RTL8365MB_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets), - RTL8365MB_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets), - RTL8365MB_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets), - RTL8365MB_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets), - RTL8365MB_MAKE_MIB_COUNTER(60, 4, ifOutOctets), - RTL8365MB_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames), - RTL8365MB_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames), - RTL8365MB_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions), - RTL8365MB_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions), - RTL8365MB_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions), - RTL8365MB_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions), - RTL8365MB_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames), - RTL8365MB_MAKE_MIB_COUNTER(78, 2, ifOutDiscards), - RTL8365MB_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards), - RTL8365MB_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts), - RTL8365MB_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts), - RTL8365MB_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts), - RTL8365MB_MAKE_MIB_COUNTER(88, 2, outOampduPkts), - RTL8365MB_MAKE_MIB_COUNTER(90, 2, inOampduPkts), - RTL8365MB_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess), - RTL8365MB_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail), - RTL8365MB_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess), - RTL8365MB_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail), - RTL8365MB_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop), - RTL8365MB_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop), - RTL8365MB_MAKE_MIB_COUNTER(106, 2, outIgmpReports), - RTL8365MB_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves), - RTL8365MB_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery), - RTL8365MB_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery), - RTL8365MB_MAKE_MIB_COUNTER(114, 2, outMldReports), - RTL8365MB_MAKE_MIB_COUNTER(116, 2, outMldLeaves), - RTL8365MB_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery), - RTL8365MB_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery), - RTL8365MB_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts), +#define RTL8367C_MAKE_MIB_COUNTER(_offset, _length, _name) \ + [RTL8367C_MIB_ ## _name] = { _offset, _length, #_name } + +static struct rtl8367c_mib_counter rtl8367c_mib_counters[] = { + RTL8367C_MAKE_MIB_COUNTER(0, 4, ifInOctets), + RTL8367C_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors), + RTL8367C_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors), + RTL8367C_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames), + RTL8367C_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes), + RTL8367C_MAKE_MIB_COUNTER(12, 2, etherStatsFragments), + RTL8367C_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers), + RTL8367C_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts), + RTL8367C_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents), + RTL8367C_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts), + RTL8367C_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts), + RTL8367C_MAKE_MIB_COUNTER(24, 2, inMldChecksumError), + RTL8367C_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError), + RTL8367C_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery), + RTL8367C_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery), + RTL8367C_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery), + RTL8367C_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery), + RTL8367C_MAKE_MIB_COUNTER(36, 2, inMldLeaves), + RTL8367C_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves), + RTL8367C_MAKE_MIB_COUNTER(40, 4, etherStatsOctets), + RTL8367C_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts), + RTL8367C_MAKE_MIB_COUNTER(46, 2, etherOversizeStats), + RTL8367C_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets), + RTL8367C_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets), + RTL8367C_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets), + RTL8367C_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets), + RTL8367C_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets), + RTL8367C_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets), + RTL8367C_MAKE_MIB_COUNTER(60, 4, ifOutOctets), + RTL8367C_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames), + RTL8367C_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames), + RTL8367C_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions), + RTL8367C_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions), + RTL8367C_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions), + RTL8367C_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions), + RTL8367C_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames), + RTL8367C_MAKE_MIB_COUNTER(78, 2, ifOutDiscards), + RTL8367C_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards), + RTL8367C_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts), + RTL8367C_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts), + RTL8367C_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts), + RTL8367C_MAKE_MIB_COUNTER(88, 2, outOampduPkts), + RTL8367C_MAKE_MIB_COUNTER(90, 2, inOampduPkts), + RTL8367C_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess), + RTL8367C_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail), + RTL8367C_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess), + RTL8367C_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail), + RTL8367C_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop), + RTL8367C_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop), + RTL8367C_MAKE_MIB_COUNTER(106, 2, outIgmpReports), + RTL8367C_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves), + RTL8367C_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery), + RTL8367C_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery), + RTL8367C_MAKE_MIB_COUNTER(114, 2, outMldReports), + RTL8367C_MAKE_MIB_COUNTER(116, 2, outMldLeaves), + RTL8367C_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery), + RTL8367C_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery), + RTL8367C_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts), }; -static_assert(ARRAY_SIZE(rtl8365mb_mib_counters) == RTL8365MB_MIB_END); +static_assert(ARRAY_SIZE(rtl8367c_mib_counters) == RTL8367C_MIB_END); -struct rtl8365mb_jam_tbl_entry { +struct rtl8367c_jam_tbl_entry { u16 reg; u16 val; }; /* Lifted from the vendor driver sources */ -static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = { +static const struct rtl8367c_jam_tbl_entry rtl8367c_init_jam_8367c[] = { { 0x13EB, 0x15BB }, { 0x1303, 0x06D6 }, { 0x1304, 0x0700 }, { 0x13E2, 0x003F }, { 0x13F9, 0x0090 }, { 0x121E, 0x03CA }, { 0x1233, 0x0352 }, { 0x1237, 0x00A0 }, { 0x123A, 0x0030 }, @@ -456,43 +445,43 @@ static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = { { 0x13F0, 0x0000 }, }; -static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = { +static const struct rtl8367c_jam_tbl_entry rtl8367c_init_jam_common[] = { { 0x1200, 0x7FCB }, { 0x0884, 0x0003 }, { 0x06EB, 0x0001 }, { 0x03Fa, 0x0007 }, { 0x08C8, 0x00C0 }, { 0x0A30, 0x020E }, { 0x0800, 0x0000 }, { 0x0802, 0x0000 }, { 0x09DA, 0x0013 }, { 0x1D32, 0x0002 }, }; -enum rtl8365mb_stp_state { - RTL8365MB_STP_STATE_DISABLED = 0, - RTL8365MB_STP_STATE_BLOCKING = 1, - RTL8365MB_STP_STATE_LEARNING = 2, - RTL8365MB_STP_STATE_FORWARDING = 3, +enum rtl8367c_stp_state { + RTL8367C_STP_STATE_DISABLED = 0, + RTL8367C_STP_STATE_BLOCKING = 1, + RTL8367C_STP_STATE_LEARNING = 2, + RTL8367C_STP_STATE_FORWARDING = 3, }; -enum rtl8365mb_cpu_insert { - RTL8365MB_CPU_INSERT_TO_ALL = 0, - RTL8365MB_CPU_INSERT_TO_TRAPPING = 1, - RTL8365MB_CPU_INSERT_TO_NONE = 2, +enum rtl8367c_cpu_insert { + RTL8367C_CPU_INSERT_TO_ALL = 0, + RTL8367C_CPU_INSERT_TO_TRAPPING = 1, + RTL8367C_CPU_INSERT_TO_NONE = 2, }; -enum rtl8365mb_cpu_position { - RTL8365MB_CPU_POS_AFTER_SA = 0, - RTL8365MB_CPU_POS_BEFORE_CRC = 1, +enum rtl8367c_cpu_position { + RTL8367C_CPU_POS_AFTER_SA = 0, + RTL8367C_CPU_POS_BEFORE_CRC = 1, }; -enum rtl8365mb_cpu_format { - RTL8365MB_CPU_FORMAT_8BYTES = 0, - RTL8365MB_CPU_FORMAT_4BYTES = 1, +enum rtl8367c_cpu_format { + RTL8367C_CPU_FORMAT_8BYTES = 0, + RTL8367C_CPU_FORMAT_4BYTES = 1, }; -enum rtl8365mb_cpu_rxlen { - RTL8365MB_CPU_RXLEN_72BYTES = 0, - RTL8365MB_CPU_RXLEN_64BYTES = 1, +enum rtl8367c_cpu_rxlen { + RTL8367C_CPU_RXLEN_72BYTES = 0, + RTL8367C_CPU_RXLEN_64BYTES = 1, }; /** - * struct rtl8365mb_cpu - CPU port configuration + * struct rtl8367c_cpu - CPU port configuration * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames * @mask: port mask of ports that parse should parse CPU tags * @trap_port: forward trapped frames to this port @@ -504,26 +493,26 @@ enum rtl8365mb_cpu_rxlen { * Represents the CPU tagging and CPU port configuration of the switch. These * settings are configurable at runtime. */ -struct rtl8365mb_cpu { +struct rtl8367c_cpu { bool enable; u32 mask; u32 trap_port; - enum rtl8365mb_cpu_insert insert; - enum rtl8365mb_cpu_position position; - enum rtl8365mb_cpu_rxlen rx_length; - enum rtl8365mb_cpu_format format; + enum rtl8367c_cpu_insert insert; + enum rtl8367c_cpu_position position; + enum rtl8367c_cpu_rxlen rx_length; + enum rtl8367c_cpu_format format; }; /** - * struct rtl8365mb_port - private per-port data + * struct rtl8367c_port - private per-port data * @priv: pointer to parent realtek_priv data * @index: DSA port index, same as dsa_port::index - * @stats: link statistics populated by rtl8365mb_stats_poll, ready for atomic - * access via rtl8365mb_get_stats64 + * @stats: link statistics populated by rtl8367c_stats_poll, ready for atomic + * access via rtl8367c_get_stats64 * @stats_lock: protect the stats structure during read/update * @mib_work: delayed work for polling MIB counters */ -struct rtl8365mb_port { +struct rtl8367c_port { struct realtek_priv *priv; unsigned int index; struct rtnl_link_stats64 stats; @@ -532,7 +521,7 @@ struct rtl8365mb_port { }; /** - * struct rtl8365mb - private chip-specific driver data + * struct rtl8367c - private chip-specific driver data * @priv: pointer to parent realtek_priv data * @irq: registered IRQ or zero * @chip_id: chip identifier @@ -547,52 +536,52 @@ struct rtl8365mb_port { * * Private data for this driver. */ -struct rtl8365mb { +struct rtl8367c { struct realtek_priv *priv; int irq; u32 chip_id; u32 chip_ver; u32 port_mask; u32 learn_limit_max; - struct rtl8365mb_cpu cpu; + struct rtl8367c_cpu cpu; struct mutex mib_lock; - struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS]; - const struct rtl8365mb_jam_tbl_entry *jam_table; + struct rtl8367c_port ports[RTL8367C_MAX_NUM_PORTS]; + const struct rtl8367c_jam_tbl_entry *jam_table; size_t jam_size; }; -static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv) +static int rtl8367c_phy_poll_busy(struct realtek_priv *priv) { u32 val; return regmap_read_poll_timeout(priv->map, - RTL8365MB_INDIRECT_ACCESS_STATUS_REG, + RTL8367C_INDIRECT_ACCESS_STATUS_REG, val, !val, 10, 100); } -static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy, +static int rtl8367c_phy_ocp_prepare(struct realtek_priv *priv, int phy, u32 ocp_addr) { u32 val; int ret; /* Set OCP prefix */ - val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr); + val = FIELD_GET(RTL8367C_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr); ret = regmap_update_bits( - priv->map, RTL8365MB_GPHY_OCP_MSB_0_REG, - RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, - FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val)); + priv->map, RTL8367C_GPHY_OCP_MSB_0_REG, + RTL8367C_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, + FIELD_PREP(RTL8367C_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val)); if (ret) return ret; /* Set PHY register address */ - val = RTL8365MB_PHY_BASE; - val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy); - val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK, + val = RTL8367C_PHY_BASE; + val |= FIELD_PREP(RTL8367C_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy); + val |= FIELD_PREP(RTL8367C_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK, ocp_addr >> 1); - val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK, + val |= FIELD_PREP(RTL8367C_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK, ocp_addr >> 6); - ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, + ret = regmap_write(priv->map, RTL8367C_INDIRECT_ACCESS_ADDRESS_REG, val); if (ret) return ret; @@ -600,35 +589,35 @@ static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy, return 0; } -static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy, +static int rtl8367c_phy_ocp_read(struct realtek_priv *priv, int phy, u32 ocp_addr, u16 *data) { u32 val; int ret; - ret = rtl8365mb_phy_poll_busy(priv); + ret = rtl8367c_phy_poll_busy(priv); if (ret) return ret; - ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); + ret = rtl8367c_phy_ocp_prepare(priv, phy, ocp_addr); if (ret) return ret; /* Execute read operation */ - val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, - RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | - FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, - RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ); - ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val); + val = FIELD_PREP(RTL8367C_INDIRECT_ACCESS_CTRL_CMD_MASK, + RTL8367C_INDIRECT_ACCESS_CTRL_CMD_VALUE) | + FIELD_PREP(RTL8367C_INDIRECT_ACCESS_CTRL_RW_MASK, + RTL8367C_INDIRECT_ACCESS_CTRL_RW_READ); + ret = regmap_write(priv->map, RTL8367C_INDIRECT_ACCESS_CTRL_REG, val); if (ret) return ret; - ret = rtl8365mb_phy_poll_busy(priv); + ret = rtl8367c_phy_poll_busy(priv); if (ret) return ret; /* Get PHY register data */ - ret = regmap_read(priv->map, RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, + ret = regmap_read(priv->map, RTL8367C_INDIRECT_ACCESS_READ_DATA_REG, &val); if (ret) return ret; @@ -638,58 +627,58 @@ static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy, return 0; } -static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy, +static int rtl8367c_phy_ocp_write(struct realtek_priv *priv, int phy, u32 ocp_addr, u16 data) { u32 val; int ret; - ret = rtl8365mb_phy_poll_busy(priv); + ret = rtl8367c_phy_poll_busy(priv); if (ret) return ret; - ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); + ret = rtl8367c_phy_ocp_prepare(priv, phy, ocp_addr); if (ret) return ret; /* Set PHY register data */ - ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, + ret = regmap_write(priv->map, RTL8367C_INDIRECT_ACCESS_WRITE_DATA_REG, data); if (ret) return ret; /* Execute write operation */ - val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, - RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | - FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, - RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE); - ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val); + val = FIELD_PREP(RTL8367C_INDIRECT_ACCESS_CTRL_CMD_MASK, + RTL8367C_INDIRECT_ACCESS_CTRL_CMD_VALUE) | + FIELD_PREP(RTL8367C_INDIRECT_ACCESS_CTRL_RW_MASK, + RTL8367C_INDIRECT_ACCESS_CTRL_RW_WRITE); + ret = regmap_write(priv->map, RTL8367C_INDIRECT_ACCESS_CTRL_REG, val); if (ret) return ret; - ret = rtl8365mb_phy_poll_busy(priv); + ret = rtl8367c_phy_poll_busy(priv); if (ret) return ret; return 0; } -static int rtl8365mb_phy_read(struct dsa_switch *ds, int phy, int regnum) +static int rtl8367c_phy_read(struct dsa_switch *ds, int phy, int regnum) { u32 ocp_addr; u16 val; int ret; struct realtek_priv *priv = ds->priv; - if (phy > RTL8365MB_PHYADDRMAX) + if (phy > RTL8367C_PHYADDRMAX) return -EINVAL; - if (regnum > RTL8365MB_PHYREGMAX) + if (regnum > RTL8367C_PHYREGMAX) return -EINVAL; - ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; + ocp_addr = RTL8367C_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; - ret = rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val); + ret = rtl8367c_phy_ocp_read(priv, phy, ocp_addr, &val); if (ret) { dev_err(priv->dev, "failed to read PHY%d reg %02x @ %04x, ret %d\n", phy, @@ -703,22 +692,22 @@ static int rtl8365mb_phy_read(struct dsa_switch *ds, int phy, int regnum) return val; } -static int rtl8365mb_phy_write(struct dsa_switch *ds, int phy, int regnum, +static int rtl8367c_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val) { u32 ocp_addr; int ret; struct realtek_priv *priv = (struct realtek_priv *)ds->priv; - if (phy > RTL8365MB_PHYADDRMAX) + if (phy > RTL8367C_PHYADDRMAX) return -EINVAL; - if (regnum > RTL8365MB_PHYREGMAX) + if (regnum > RTL8367C_PHYREGMAX) return -EINVAL; - ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; + ocp_addr = RTL8367C_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; - ret = rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val); + ret = rtl8367c_phy_ocp_write(priv, phy, ocp_addr, val); if (ret) { dev_err(priv->dev, "failed to write PHY%d reg %02x @ %04x, ret %d\n", phy, @@ -733,13 +722,13 @@ static int rtl8365mb_phy_write(struct dsa_switch *ds, int phy, int regnum, } static enum dsa_tag_protocol -rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port, +rtl8367c_get_tag_protocol(struct dsa_switch *ds, int port, enum dsa_tag_protocol mp) { return DSA_TAG_PROTO_RTL8_4; } -static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, +static int rtl8367c_ext_config_rgmii(struct realtek_priv *priv, int port, phy_interface_t interface) { struct device_node *dn; @@ -774,7 +763,7 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, * * The vendor driver also states that this must be configured *before* * forcing the external interface into a particular mode, which is done - * in the rtl8365mb_phylink_mac_link_{up,down} functions. + * in the rtl8367c_phylink_mac_link_{up,down} functions. * * Only configure an RGMII TX (resp. RX) delay if the * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is @@ -803,19 +792,19 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, } ret = regmap_update_bits( - priv->map, RTL8365MB_EXT_RGMXF_REG(ext_port), - RTL8365MB_EXT_RGMXF_TXDELAY_MASK | - RTL8365MB_EXT_RGMXF_RXDELAY_MASK, - FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) | - FIELD_PREP(RTL8365MB_EXT_RGMXF_RXDELAY_MASK, rx_delay)); + priv->map, RTL8367C_EXT_RGMXF_REG(ext_port), + RTL8367C_EXT_RGMXF_TXDELAY_MASK | + RTL8367C_EXT_RGMXF_RXDELAY_MASK, + FIELD_PREP(RTL8367C_EXT_RGMXF_TXDELAY_MASK, tx_delay) | + FIELD_PREP(RTL8367C_EXT_RGMXF_RXDELAY_MASK, rx_delay)); if (ret) return ret; ret = regmap_update_bits( - priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(ext_port), - RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(ext_port), - RTL8365MB_EXT_PORT_MODE_RGMII - << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET( + priv->map, RTL8367C_DIGITAL_INTERFACE_SELECT_REG(ext_port), + RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_MASK(ext_port), + RTL8367C_EXT_PORT_MODE_RGMII + << RTL8367C_DIGITAL_INTERFACE_SELECT_MODE_OFFSET( ext_port)); if (ret) return ret; @@ -823,7 +812,7 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, return 0; } -static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, +static int rtl8367c_ext_config_forcemode(struct realtek_priv *priv, int port, bool link, int speed, int duplex, bool tx_pause, bool rx_pause) { @@ -850,11 +839,11 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, r_tx_pause = tx_pause ? 1 : 0; if (speed == SPEED_1000) { - r_speed = RTL8365MB_PORT_SPEED_1000M; + r_speed = RTL8367C_PORT_SPEED_1000M; } else if (speed == SPEED_100) { - r_speed = RTL8365MB_PORT_SPEED_100M; + r_speed = RTL8367C_PORT_SPEED_100M; } else if (speed == SPEED_10) { - r_speed = RTL8365MB_PORT_SPEED_10M; + r_speed = RTL8367C_PORT_SPEED_10M; } else { dev_err(priv->dev, "unsupported port speed %s\n", phy_speed_to_str(speed)); @@ -879,17 +868,17 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, r_duplex = 0; } - val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) | - FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK, + val = FIELD_PREP(RTL8367C_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) | + FIELD_PREP(RTL8367C_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK, r_tx_pause) | - FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK, + FIELD_PREP(RTL8367C_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK, r_rx_pause) | - FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) | - FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK, + FIELD_PREP(RTL8367C_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) | + FIELD_PREP(RTL8367C_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK, r_duplex) | - FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); + FIELD_PREP(RTL8367C_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); ret = regmap_write(priv->map, - RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(ext_port), + RTL8367C_DIGITAL_INTERFACE_FORCE_REG(ext_port), val); if (ret) return ret; @@ -897,7 +886,7 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, return 0; } -static bool rtl8365mb_phy_mode_supported(struct dsa_switch *ds, int port, +static bool rtl8367c_phy_mode_supported(struct dsa_switch *ds, int port, phy_interface_t interface) { if (dsa_is_user_port(ds, port) && @@ -914,7 +903,7 @@ static bool rtl8365mb_phy_mode_supported(struct dsa_switch *ds, int port, return false; } -static void rtl8365mb_phylink_validate(struct dsa_switch *ds, int port, +static void rtl8367c_phylink_validate(struct dsa_switch *ds, int port, unsigned long *supported, struct phylink_link_state *state) { @@ -926,7 +915,7 @@ static void rtl8365mb_phylink_validate(struct dsa_switch *ds, int port, * expects the MAC driver to return all supported link modes. */ if (state->interface != PHY_INTERFACE_MODE_NA && - !rtl8365mb_phy_mode_supported(ds, port, state->interface)) { + !rtl8367c_phy_mode_supported(ds, port, state->interface)) { dev_err(priv->dev, "phy mode %s is unsupported on port %d\n", phy_modes(state->interface), port); linkmode_zero(supported); @@ -949,14 +938,14 @@ static void rtl8365mb_phylink_validate(struct dsa_switch *ds, int port, linkmode_and(state->advertising, state->advertising, mask); } -static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port, +static void rtl8367c_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) { struct realtek_priv *priv = ds->priv; int ret; - if (!rtl8365mb_phy_mode_supported(ds, port, state->interface)) { + if (!rtl8367c_phy_mode_supported(ds, port, state->interface)) { dev_err(priv->dev, "phy mode %s is unsupported on port %d\n", phy_modes(state->interface), port); return; @@ -970,7 +959,7 @@ static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port, } if (phy_interface_mode_is_rgmii(state->interface)) { - ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface); + ret = rtl8367c_ext_config_rgmii(priv, port, state->interface); if (ret) dev_err(priv->dev, "failed to configure RGMII mode on port %d: %d\n", @@ -983,13 +972,13 @@ static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port, */ } -static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port, +static void rtl8367c_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { struct realtek_priv *priv = ds->priv; - struct rtl8365mb_port *p; - struct rtl8365mb *mb; + struct rtl8367c_port *p; + struct rtl8367c *mb; int ret; mb = priv->chip_data; @@ -997,7 +986,7 @@ static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port, cancel_delayed_work_sync(&p->mib_work); if (phy_interface_mode_is_rgmii(interface)) { - ret = rtl8365mb_ext_config_forcemode(priv, port, false, 0, 0, + ret = rtl8367c_ext_config_forcemode(priv, port, false, 0, 0, false, false); if (ret) dev_err(priv->dev, @@ -1008,7 +997,7 @@ static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port, } } -static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port, +static void rtl8367c_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface, struct phy_device *phydev, int speed, @@ -1016,8 +1005,8 @@ static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port, bool rx_pause) { struct realtek_priv *priv = ds->priv; - struct rtl8365mb_port *p; - struct rtl8365mb *mb; + struct rtl8367c_port *p; + struct rtl8367c *mb; int ret; mb = priv->chip_data; @@ -1025,7 +1014,7 @@ static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port, schedule_delayed_work(&p->mib_work, 0); if (phy_interface_mode_is_rgmii(interface)) { - ret = rtl8365mb_ext_config_forcemode(priv, port, true, speed, + ret = rtl8367c_ext_config_forcemode(priv, port, true, speed, duplex, tx_pause, rx_pause); if (ret) @@ -1037,58 +1026,58 @@ static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port, } } -static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port, +static void rtl8367c_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) { struct realtek_priv *priv = ds->priv; - enum rtl8365mb_stp_state val; + enum rtl8367c_stp_state val; int msti = 0; switch (state) { case BR_STATE_DISABLED: - val = RTL8365MB_STP_STATE_DISABLED; + val = RTL8367C_STP_STATE_DISABLED; break; case BR_STATE_BLOCKING: case BR_STATE_LISTENING: - val = RTL8365MB_STP_STATE_BLOCKING; + val = RTL8367C_STP_STATE_BLOCKING; break; case BR_STATE_LEARNING: - val = RTL8365MB_STP_STATE_LEARNING; + val = RTL8367C_STP_STATE_LEARNING; break; case BR_STATE_FORWARDING: - val = RTL8365MB_STP_STATE_FORWARDING; + val = RTL8367C_STP_STATE_FORWARDING; break; default: dev_err(priv->dev, "invalid STP state: %u\n", state); return; } - regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port), - RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(port), - val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port)); + regmap_update_bits(priv->map, RTL8367C_MSTI_CTRL_REG(msti, port), + RTL8367C_MSTI_CTRL_PORT_STATE_MASK(port), + val << RTL8367C_MSTI_CTRL_PORT_STATE_OFFSET(port)); } -static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port, +static int rtl8367c_port_set_learning(struct realtek_priv *priv, int port, bool enable) { - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; /* Enable/disable learning by limiting the number of L2 addresses the * port can learn. Realtek documentation states that a limit of zero * disables learning. When enabling learning, set it to the chip's * maximum. */ - return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port), + return regmap_write(priv->map, RTL8367C_LUT_PORT_LEARN_LIMIT_REG(port), enable ? mb->learn_limit_max : 0); } -static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port, +static int rtl8367c_port_set_isolation(struct realtek_priv *priv, int port, u32 mask) { - return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask); + return regmap_write(priv->map, RTL8367C_PORT_ISOLATION_REG(port), mask); } -static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, +static int rtl8367c_mib_counter_read(struct realtek_priv *priv, int port, u32 offset, u32 length, u64 *mibvalue) { u64 tmpvalue = 0; @@ -1100,20 +1089,20 @@ static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, * and then poll the control register before reading the value from some * counter registers. */ - ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG, - RTL8365MB_MIB_ADDRESS(port, offset)); + ret = regmap_write(priv->map, RTL8367C_MIB_ADDRESS_REG, + RTL8367C_MIB_ADDRESS(port, offset)); if (ret) return ret; /* Poll for completion */ - ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val, - !(val & RTL8365MB_MIB_CTRL0_BUSY_MASK), + ret = regmap_read_poll_timeout(priv->map, RTL8367C_MIB_CTRL0_REG, val, + !(val & RTL8367C_MIB_CTRL0_BUSY_MASK), 10, 100); if (ret) return ret; /* Presumably this indicates a MIB counter read failure */ - if (val & RTL8365MB_MIB_CTRL0_RESET_MASK) + if (val & RTL8367C_MIB_CTRL0_RESET_MASK) return -EIO; /* There are four MIB counter registers each holding a 16 bit word of a @@ -1129,7 +1118,7 @@ static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, /* Read the MIB counter 16 bits at a time */ for (i = 0; i < length; i++) { ret = regmap_read(priv->map, - RTL8365MB_MIB_COUNTER_REG(offset - i), &val); + RTL8367C_MIB_COUNTER_REG(offset - i), &val); if (ret) return ret; @@ -1142,20 +1131,20 @@ static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, return 0; } -static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) +static void rtl8367c_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) { struct realtek_priv *priv = ds->priv; - struct rtl8365mb *mb; + struct rtl8367c *mb; int ret; int i; mb = priv->chip_data; mutex_lock(&mb->mib_lock); - for (i = 0; i < RTL8365MB_MIB_END; i++) { - struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; + for (i = 0; i < RTL8367C_MIB_END; i++) { + struct rtl8367c_mib_counter *mib = &rtl8367c_mib_counters[i]; - ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, + ret = rtl8367c_mib_counter_read(priv, port, mib->offset, mib->length, &data[i]); if (ret) { dev_err(priv->dev, @@ -1167,83 +1156,83 @@ static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *da mutex_unlock(&mb->mib_lock); } -static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data) +static void rtl8367c_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data) { int i; if (stringset != ETH_SS_STATS) return; - for (i = 0; i < RTL8365MB_MIB_END; i++) { - struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; + for (i = 0; i < RTL8367C_MIB_END; i++) { + struct rtl8367c_mib_counter *mib = &rtl8367c_mib_counters[i]; strncpy(data + i * ETH_GSTRING_LEN, mib->name, ETH_GSTRING_LEN); } } -static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset) +static int rtl8367c_get_sset_count(struct dsa_switch *ds, int port, int sset) { if (sset != ETH_SS_STATS) return -EOPNOTSUPP; - return RTL8365MB_MIB_END; + return RTL8367C_MIB_END; } -static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port, +static void rtl8367c_get_phy_stats(struct dsa_switch *ds, int port, struct ethtool_eth_phy_stats *phy_stats) { struct realtek_priv *priv = ds->priv; - struct rtl8365mb_mib_counter *mib; - struct rtl8365mb *mb; + struct rtl8367c_mib_counter *mib; + struct rtl8367c *mb; mb = priv->chip_data; - mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3StatsSymbolErrors]; + mib = &rtl8367c_mib_counters[RTL8367C_MIB_dot3StatsSymbolErrors]; mutex_lock(&mb->mib_lock); - rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, + rtl8367c_mib_counter_read(priv, port, mib->offset, mib->length, &phy_stats->SymbolErrorDuringCarrier); mutex_unlock(&mb->mib_lock); } -static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port, +static void rtl8367c_get_mac_stats(struct dsa_switch *ds, int port, struct ethtool_eth_mac_stats *mac_stats) { - u64 cnt[RTL8365MB_MIB_END] = { - [RTL8365MB_MIB_ifOutOctets] = 1, - [RTL8365MB_MIB_ifOutUcastPkts] = 1, - [RTL8365MB_MIB_ifOutMulticastPkts] = 1, - [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, - [RTL8365MB_MIB_dot3OutPauseFrames] = 1, - [RTL8365MB_MIB_ifOutDiscards] = 1, - [RTL8365MB_MIB_ifInOctets] = 1, - [RTL8365MB_MIB_ifInUcastPkts] = 1, - [RTL8365MB_MIB_ifInMulticastPkts] = 1, - [RTL8365MB_MIB_ifInBroadcastPkts] = 1, - [RTL8365MB_MIB_dot3InPauseFrames] = 1, - [RTL8365MB_MIB_dot3StatsSingleCollisionFrames] = 1, - [RTL8365MB_MIB_dot3StatsMultipleCollisionFrames] = 1, - [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, - [RTL8365MB_MIB_dot3StatsDeferredTransmissions] = 1, - [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, - [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1, + u64 cnt[RTL8367C_MIB_END] = { + [RTL8367C_MIB_ifOutOctets] = 1, + [RTL8367C_MIB_ifOutUcastPkts] = 1, + [RTL8367C_MIB_ifOutMulticastPkts] = 1, + [RTL8367C_MIB_ifOutBroadcastPkts] = 1, + [RTL8367C_MIB_dot3OutPauseFrames] = 1, + [RTL8367C_MIB_ifOutDiscards] = 1, + [RTL8367C_MIB_ifInOctets] = 1, + [RTL8367C_MIB_ifInUcastPkts] = 1, + [RTL8367C_MIB_ifInMulticastPkts] = 1, + [RTL8367C_MIB_ifInBroadcastPkts] = 1, + [RTL8367C_MIB_dot3InPauseFrames] = 1, + [RTL8367C_MIB_dot3StatsSingleCollisionFrames] = 1, + [RTL8367C_MIB_dot3StatsMultipleCollisionFrames] = 1, + [RTL8367C_MIB_dot3StatsFCSErrors] = 1, + [RTL8367C_MIB_dot3StatsDeferredTransmissions] = 1, + [RTL8367C_MIB_dot3StatsLateCollisions] = 1, + [RTL8367C_MIB_dot3StatsExcessiveCollisions] = 1, }; struct realtek_priv *priv = ds->priv; - struct rtl8365mb *mb; + struct rtl8367c *mb; int ret; int i; mb = priv->chip_data; mutex_lock(&mb->mib_lock); - for (i = 0; i < RTL8365MB_MIB_END; i++) { - struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; + for (i = 0; i < RTL8367C_MIB_END; i++) { + struct rtl8367c_mib_counter *mib = &rtl8367c_mib_counters[i]; /* Only fetch required MIB counters (marked = 1 above) */ if (!cnt[i]) continue; - ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, + ret = rtl8367c_mib_counter_read(priv, port, mib->offset, mib->length, &cnt[i]); if (ret) break; @@ -1256,76 +1245,76 @@ static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port, * subject. */ - mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] + - cnt[RTL8365MB_MIB_ifOutMulticastPkts] + - cnt[RTL8365MB_MIB_ifOutBroadcastPkts] + - cnt[RTL8365MB_MIB_dot3OutPauseFrames] - - cnt[RTL8365MB_MIB_ifOutDiscards]; + mac_stats->FramesTransmittedOK = cnt[RTL8367C_MIB_ifOutUcastPkts] + + cnt[RTL8367C_MIB_ifOutMulticastPkts] + + cnt[RTL8367C_MIB_ifOutBroadcastPkts] + + cnt[RTL8367C_MIB_dot3OutPauseFrames] - + cnt[RTL8367C_MIB_ifOutDiscards]; mac_stats->SingleCollisionFrames = - cnt[RTL8365MB_MIB_dot3StatsSingleCollisionFrames]; + cnt[RTL8367C_MIB_dot3StatsSingleCollisionFrames]; mac_stats->MultipleCollisionFrames = - cnt[RTL8365MB_MIB_dot3StatsMultipleCollisionFrames]; - mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] + - cnt[RTL8365MB_MIB_ifInMulticastPkts] + - cnt[RTL8365MB_MIB_ifInBroadcastPkts] + - cnt[RTL8365MB_MIB_dot3InPauseFrames]; + cnt[RTL8367C_MIB_dot3StatsMultipleCollisionFrames]; + mac_stats->FramesReceivedOK = cnt[RTL8367C_MIB_ifInUcastPkts] + + cnt[RTL8367C_MIB_ifInMulticastPkts] + + cnt[RTL8367C_MIB_ifInBroadcastPkts] + + cnt[RTL8367C_MIB_dot3InPauseFrames]; mac_stats->FrameCheckSequenceErrors = - cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; - mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] - + cnt[RTL8367C_MIB_dot3StatsFCSErrors]; + mac_stats->OctetsTransmittedOK = cnt[RTL8367C_MIB_ifOutOctets] - 18 * mac_stats->FramesTransmittedOK; mac_stats->FramesWithDeferredXmissions = - cnt[RTL8365MB_MIB_dot3StatsDeferredTransmissions]; - mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; + cnt[RTL8367C_MIB_dot3StatsDeferredTransmissions]; + mac_stats->LateCollisions = cnt[RTL8367C_MIB_dot3StatsLateCollisions]; mac_stats->FramesAbortedDueToXSColls = - cnt[RTL8365MB_MIB_dot3StatsExcessiveCollisions]; - mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] - + cnt[RTL8367C_MIB_dot3StatsExcessiveCollisions]; + mac_stats->OctetsReceivedOK = cnt[RTL8367C_MIB_ifInOctets] - 18 * mac_stats->FramesReceivedOK; mac_stats->MulticastFramesXmittedOK = - cnt[RTL8365MB_MIB_ifOutMulticastPkts]; + cnt[RTL8367C_MIB_ifOutMulticastPkts]; mac_stats->BroadcastFramesXmittedOK = - cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; + cnt[RTL8367C_MIB_ifOutBroadcastPkts]; mac_stats->MulticastFramesReceivedOK = - cnt[RTL8365MB_MIB_ifInMulticastPkts]; + cnt[RTL8367C_MIB_ifInMulticastPkts]; mac_stats->BroadcastFramesReceivedOK = - cnt[RTL8365MB_MIB_ifInBroadcastPkts]; + cnt[RTL8367C_MIB_ifInBroadcastPkts]; } -static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port, +static void rtl8367c_get_ctrl_stats(struct dsa_switch *ds, int port, struct ethtool_eth_ctrl_stats *ctrl_stats) { struct realtek_priv *priv = ds->priv; - struct rtl8365mb_mib_counter *mib; - struct rtl8365mb *mb; + struct rtl8367c_mib_counter *mib; + struct rtl8367c *mb; mb = priv->chip_data; - mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3ControlInUnknownOpcodes]; + mib = &rtl8367c_mib_counters[RTL8367C_MIB_dot3ControlInUnknownOpcodes]; mutex_lock(&mb->mib_lock); - rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, + rtl8367c_mib_counter_read(priv, port, mib->offset, mib->length, &ctrl_stats->UnsupportedOpcodesReceived); mutex_unlock(&mb->mib_lock); } -static void rtl8365mb_stats_update(struct realtek_priv *priv, int port) +static void rtl8367c_stats_update(struct realtek_priv *priv, int port) { - u64 cnt[RTL8365MB_MIB_END] = { - [RTL8365MB_MIB_ifOutOctets] = 1, - [RTL8365MB_MIB_ifOutUcastPkts] = 1, - [RTL8365MB_MIB_ifOutMulticastPkts] = 1, - [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, - [RTL8365MB_MIB_ifOutDiscards] = 1, - [RTL8365MB_MIB_ifInOctets] = 1, - [RTL8365MB_MIB_ifInUcastPkts] = 1, - [RTL8365MB_MIB_ifInMulticastPkts] = 1, - [RTL8365MB_MIB_ifInBroadcastPkts] = 1, - [RTL8365MB_MIB_etherStatsDropEvents] = 1, - [RTL8365MB_MIB_etherStatsCollisions] = 1, - [RTL8365MB_MIB_etherStatsFragments] = 1, - [RTL8365MB_MIB_etherStatsJabbers] = 1, - [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, - [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, + u64 cnt[RTL8367C_MIB_END] = { + [RTL8367C_MIB_ifOutOctets] = 1, + [RTL8367C_MIB_ifOutUcastPkts] = 1, + [RTL8367C_MIB_ifOutMulticastPkts] = 1, + [RTL8367C_MIB_ifOutBroadcastPkts] = 1, + [RTL8367C_MIB_ifOutDiscards] = 1, + [RTL8367C_MIB_ifInOctets] = 1, + [RTL8367C_MIB_ifInUcastPkts] = 1, + [RTL8367C_MIB_ifInMulticastPkts] = 1, + [RTL8367C_MIB_ifInBroadcastPkts] = 1, + [RTL8367C_MIB_etherStatsDropEvents] = 1, + [RTL8367C_MIB_etherStatsCollisions] = 1, + [RTL8367C_MIB_etherStatsFragments] = 1, + [RTL8367C_MIB_etherStatsJabbers] = 1, + [RTL8367C_MIB_dot3StatsFCSErrors] = 1, + [RTL8367C_MIB_dot3StatsLateCollisions] = 1, }; - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; struct rtnl_link_stats64 *stats; int ret; int i; @@ -1333,14 +1322,14 @@ static void rtl8365mb_stats_update(struct realtek_priv *priv, int port) stats = &mb->ports[port].stats; mutex_lock(&mb->mib_lock); - for (i = 0; i < RTL8365MB_MIB_END; i++) { - struct rtl8365mb_mib_counter *c = &rtl8365mb_mib_counters[i]; + for (i = 0; i < RTL8367C_MIB_END; i++) { + struct rtl8367c_mib_counter *c = &rtl8367c_mib_counters[i]; /* Only fetch required MIB counters (marked = 1 above) */ if (!cnt[i]) continue; - ret = rtl8365mb_mib_counter_read(priv, port, c->offset, + ret = rtl8367c_mib_counter_read(priv, port, c->offset, c->length, &cnt[i]); if (ret) break; @@ -1353,56 +1342,56 @@ static void rtl8365mb_stats_update(struct realtek_priv *priv, int port) spin_lock(&mb->ports[port].stats_lock); - stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] + - cnt[RTL8365MB_MIB_ifInMulticastPkts] + - cnt[RTL8365MB_MIB_ifInBroadcastPkts] - - cnt[RTL8365MB_MIB_ifOutDiscards]; + stats->rx_packets = cnt[RTL8367C_MIB_ifInUcastPkts] + + cnt[RTL8367C_MIB_ifInMulticastPkts] + + cnt[RTL8367C_MIB_ifInBroadcastPkts] - + cnt[RTL8367C_MIB_ifOutDiscards]; - stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] + - cnt[RTL8365MB_MIB_ifOutMulticastPkts] + - cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; + stats->tx_packets = cnt[RTL8367C_MIB_ifOutUcastPkts] + + cnt[RTL8367C_MIB_ifOutMulticastPkts] + + cnt[RTL8367C_MIB_ifOutBroadcastPkts]; /* if{In,Out}Octets includes FCS - remove it */ - stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets; + stats->rx_bytes = cnt[RTL8367C_MIB_ifInOctets] - 4 * stats->rx_packets; stats->tx_bytes = - cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets; + cnt[RTL8367C_MIB_ifOutOctets] - 4 * stats->tx_packets; - stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents]; - stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards]; + stats->rx_dropped = cnt[RTL8367C_MIB_etherStatsDropEvents]; + stats->tx_dropped = cnt[RTL8367C_MIB_ifOutDiscards]; - stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts]; - stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions]; + stats->multicast = cnt[RTL8367C_MIB_ifInMulticastPkts]; + stats->collisions = cnt[RTL8367C_MIB_etherStatsCollisions]; - stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] + - cnt[RTL8365MB_MIB_etherStatsJabbers]; - stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; + stats->rx_length_errors = cnt[RTL8367C_MIB_etherStatsFragments] + + cnt[RTL8367C_MIB_etherStatsJabbers]; + stats->rx_crc_errors = cnt[RTL8367C_MIB_dot3StatsFCSErrors]; stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors; - stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards]; - stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; + stats->tx_aborted_errors = cnt[RTL8367C_MIB_ifOutDiscards]; + stats->tx_window_errors = cnt[RTL8367C_MIB_dot3StatsLateCollisions]; stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors; spin_unlock(&mb->ports[port].stats_lock); } -static void rtl8365mb_stats_poll(struct work_struct *work) +static void rtl8367c_stats_poll(struct work_struct *work) { - struct rtl8365mb_port *p = container_of(to_delayed_work(work), - struct rtl8365mb_port, + struct rtl8367c_port *p = container_of(to_delayed_work(work), + struct rtl8367c_port, mib_work); struct realtek_priv *priv = p->priv; - rtl8365mb_stats_update(priv, p->index); + rtl8367c_stats_update(priv, p->index); - schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES); + schedule_delayed_work(&p->mib_work, RTL8367C_STATS_INTERVAL_JIFFIES); } -static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port, +static void rtl8367c_get_stats64(struct dsa_switch *ds, int port, struct rtnl_link_stats64 *s) { struct realtek_priv *priv = ds->priv; - struct rtl8365mb_port *p; - struct rtl8365mb *mb; + struct rtl8367c_port *p; + struct rtl8367c *mb; mb = priv->chip_data; p = &mb->ports[port]; @@ -1412,9 +1401,9 @@ static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port, spin_unlock(&p->stats_lock); } -static void rtl8365mb_stats_setup(struct realtek_priv *priv) +static void rtl8367c_stats_setup(struct realtek_priv *priv) { - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; int i; /* Per-chip global mutex to protect MIB counter access, since doing @@ -1423,7 +1412,7 @@ static void rtl8365mb_stats_setup(struct realtek_priv *priv) mutex_init(&mb->mib_lock); for (i = 0; i < priv->num_ports; i++) { - struct rtl8365mb_port *p = &mb->ports[i]; + struct rtl8367c_port *p = &mb->ports[i]; if (dsa_is_unused_port(priv->ds, i)) continue; @@ -1434,17 +1423,17 @@ static void rtl8365mb_stats_setup(struct realtek_priv *priv) /* This work polls the MIB counters and keeps the stats64 data * up-to-date. */ - INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll); + INIT_DELAYED_WORK(&p->mib_work, rtl8367c_stats_poll); } } -static void rtl8365mb_stats_teardown(struct realtek_priv *priv) +static void rtl8367c_stats_teardown(struct realtek_priv *priv) { - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; int i; for (i = 0; i < priv->num_ports; i++) { - struct rtl8365mb_port *p = &mb->ports[i]; + struct rtl8367c_port *p = &mb->ports[i]; if (dsa_is_unused_port(priv->ds, i)) continue; @@ -1453,7 +1442,7 @@ static void rtl8365mb_stats_teardown(struct realtek_priv *priv) } } -static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg, +static int rtl8367c_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg, u32 *val) { int ret; @@ -1465,40 +1454,40 @@ static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg return regmap_write(priv->map, reg, *val); } -static irqreturn_t rtl8365mb_irq(int irq, void *data) +static irqreturn_t rtl8367c_irq(int irq, void *data) { struct realtek_priv *priv = data; unsigned long line_changes = 0; - struct rtl8365mb *mb; + struct rtl8367c *mb; u32 stat; int line; int ret; mb = priv->chip_data; - ret = rtl8365mb_get_and_clear_status_reg(priv, RTL8365MB_INTR_STATUS_REG, + ret = rtl8367c_get_and_clear_status_reg(priv, RTL8367C_INTR_STATUS_REG, &stat); if (ret) goto out_error; - if (stat & RTL8365MB_INTR_LINK_CHANGE_MASK) { + if (stat & RTL8367C_INTR_LINK_CHANGE_MASK) { u32 linkdown_ind; u32 linkup_ind; u32 val; - ret = rtl8365mb_get_and_clear_status_reg( - priv, RTL8365MB_PORT_LINKUP_IND_REG, &val); + ret = rtl8367c_get_and_clear_status_reg( + priv, RTL8367C_PORT_LINKUP_IND_REG, &val); if (ret) goto out_error; - linkup_ind = FIELD_GET(RTL8365MB_PORT_LINKUP_IND_MASK, val); + linkup_ind = FIELD_GET(RTL8367C_PORT_LINKUP_IND_MASK, val); - ret = rtl8365mb_get_and_clear_status_reg( - priv, RTL8365MB_PORT_LINKDOWN_IND_REG, &val); + ret = rtl8367c_get_and_clear_status_reg( + priv, RTL8367C_PORT_LINKDOWN_IND_REG, &val); if (ret) goto out_error; - linkdown_ind = FIELD_GET(RTL8365MB_PORT_LINKDOWN_IND_MASK, val); + linkdown_ind = FIELD_GET(RTL8367C_PORT_LINKDOWN_IND_MASK, val); line_changes = (linkup_ind | linkdown_ind) & mb->port_mask; } @@ -1521,56 +1510,56 @@ static irqreturn_t rtl8365mb_irq(int irq, void *data) return IRQ_NONE; } -static struct irq_chip rtl8365mb_irq_chip = { - .name = "rtl8365mb", +static struct irq_chip rtl8367c_irq_chip = { + .name = "rtl8367c", /* The hardware doesn't support masking IRQs on a per-port basis */ }; -static int rtl8365mb_irq_map(struct irq_domain *domain, unsigned int irq, +static int rtl8367c_irq_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) { irq_set_chip_data(irq, domain->host_data); - irq_set_chip_and_handler(irq, &rtl8365mb_irq_chip, handle_simple_irq); + irq_set_chip_and_handler(irq, &rtl8367c_irq_chip, handle_simple_irq); irq_set_nested_thread(irq, 1); irq_set_noprobe(irq); return 0; } -static void rtl8365mb_irq_unmap(struct irq_domain *d, unsigned int irq) +static void rtl8367c_irq_unmap(struct irq_domain *d, unsigned int irq) { irq_set_nested_thread(irq, 0); irq_set_chip_and_handler(irq, NULL, NULL); irq_set_chip_data(irq, NULL); } -static const struct irq_domain_ops rtl8365mb_irqdomain_ops = { - .map = rtl8365mb_irq_map, - .unmap = rtl8365mb_irq_unmap, +static const struct irq_domain_ops rtl8367c_irqdomain_ops = { + .map = rtl8367c_irq_map, + .unmap = rtl8367c_irq_unmap, .xlate = irq_domain_xlate_onecell, }; -static int rtl8365mb_set_irq_enable(struct realtek_priv *priv, bool enable) +static int rtl8367c_set_irq_enable(struct realtek_priv *priv, bool enable) { - return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG, - RTL8365MB_INTR_LINK_CHANGE_MASK, - FIELD_PREP(RTL8365MB_INTR_LINK_CHANGE_MASK, + return regmap_update_bits(priv->map, RTL8367C_INTR_CTRL_REG, + RTL8367C_INTR_LINK_CHANGE_MASK, + FIELD_PREP(RTL8367C_INTR_LINK_CHANGE_MASK, enable ? 1 : 0)); } -static int rtl8365mb_irq_enable(struct realtek_priv *priv) +static int rtl8367c_irq_enable(struct realtek_priv *priv) { - return rtl8365mb_set_irq_enable(priv, true); + return rtl8367c_set_irq_enable(priv, true); } -static int rtl8365mb_irq_disable(struct realtek_priv *priv) +static int rtl8367c_irq_disable(struct realtek_priv *priv) { - return rtl8365mb_set_irq_enable(priv, false); + return rtl8367c_set_irq_enable(priv, false); } -static int rtl8365mb_irq_setup(struct realtek_priv *priv) +static int rtl8367c_irq_setup(struct realtek_priv *priv) { - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; struct device_node *intc; u32 irq_trig; int virq; @@ -1585,7 +1574,7 @@ static int rtl8365mb_irq_setup(struct realtek_priv *priv) return -EINVAL; } - /* rtl8365mb IRQs cascade off this one */ + /* rtl8367c IRQs cascade off this one */ irq = of_irq_get(intc, 0); if (irq <= 0) { if (irq != -EPROBE_DEFER) @@ -1596,7 +1585,7 @@ static int rtl8365mb_irq_setup(struct realtek_priv *priv) } priv->irqdomain = irq_domain_add_linear(intc, priv->num_ports, - &rtl8365mb_irqdomain_ops, priv); + &rtl8367c_irqdomain_ops, priv); if (!priv->irqdomain) { dev_err(priv->dev, "failed to add irq domain\n"); ret = -ENOMEM; @@ -1620,11 +1609,11 @@ static int rtl8365mb_irq_setup(struct realtek_priv *priv) switch (irq_trig) { case IRQF_TRIGGER_RISING: case IRQF_TRIGGER_HIGH: - val = RTL8365MB_INTR_POLARITY_HIGH; + val = RTL8367C_INTR_POLARITY_HIGH; break; case IRQF_TRIGGER_FALLING: case IRQF_TRIGGER_LOW: - val = RTL8365MB_INTR_POLARITY_LOW; + val = RTL8367C_INTR_POLARITY_LOW; break; default: dev_err(priv->dev, "unsupported irq trigger type %u\n", @@ -1633,25 +1622,25 @@ static int rtl8365mb_irq_setup(struct realtek_priv *priv) goto out_remove_irqdomain; } - ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG, - RTL8365MB_INTR_POLARITY_MASK, - FIELD_PREP(RTL8365MB_INTR_POLARITY_MASK, val)); + ret = regmap_update_bits(priv->map, RTL8367C_INTR_POLARITY_REG, + RTL8367C_INTR_POLARITY_MASK, + FIELD_PREP(RTL8367C_INTR_POLARITY_MASK, val)); if (ret) goto out_remove_irqdomain; /* Disable the interrupt in case the chip has it enabled on reset */ - ret = rtl8365mb_irq_disable(priv); + ret = rtl8367c_irq_disable(priv); if (ret) goto out_remove_irqdomain; /* Clear the interrupt status register */ - ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG, - RTL8365MB_INTR_ALL_MASK); + ret = regmap_write(priv->map, RTL8367C_INTR_STATUS_REG, + RTL8367C_INTR_ALL_MASK); if (ret) goto out_remove_irqdomain; - ret = request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT, - "rtl8365mb", priv); + ret = request_threaded_irq(irq, NULL, rtl8367c_irq, IRQF_ONESHOT, + "rtl8367c", priv); if (ret) { dev_err(priv->dev, "failed to request irq: %d\n", ret); goto out_remove_irqdomain; @@ -1660,7 +1649,7 @@ static int rtl8365mb_irq_setup(struct realtek_priv *priv) /* Store the irq so that we know to free it during teardown */ mb->irq = irq; - ret = rtl8365mb_irq_enable(priv); + ret = rtl8367c_irq_enable(priv); if (ret) goto out_free_irq; @@ -1687,9 +1676,9 @@ static int rtl8365mb_irq_setup(struct realtek_priv *priv) return ret; } -static void rtl8365mb_irq_teardown(struct realtek_priv *priv) +static void rtl8367c_irq_teardown(struct realtek_priv *priv) { - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; int virq; int i; @@ -1709,38 +1698,38 @@ static void rtl8365mb_irq_teardown(struct realtek_priv *priv) } } -static int rtl8365mb_cpu_config(struct realtek_priv *priv) +static int rtl8367c_cpu_config(struct realtek_priv *priv) { - struct rtl8365mb *mb = priv->chip_data; - struct rtl8365mb_cpu *cpu = &mb->cpu; + struct rtl8367c *mb = priv->chip_data; + struct rtl8367c_cpu *cpu = &mb->cpu; u32 val; int ret; - ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG, - RTL8365MB_CPU_PORT_MASK_MASK, - FIELD_PREP(RTL8365MB_CPU_PORT_MASK_MASK, + ret = regmap_update_bits(priv->map, RTL8367C_CPU_PORT_MASK_REG, + RTL8367C_CPU_PORT_MASK_MASK, + FIELD_PREP(RTL8367C_CPU_PORT_MASK_MASK, cpu->mask)); if (ret) return ret; - val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) | - FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) | - FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) | - FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) | - FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) | - FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port) | - FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK, + val = FIELD_PREP(RTL8367C_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) | + FIELD_PREP(RTL8367C_CPU_CTRL_INSERTMODE_MASK, cpu->insert) | + FIELD_PREP(RTL8367C_CPU_CTRL_TAG_POSITION_MASK, cpu->position) | + FIELD_PREP(RTL8367C_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) | + FIELD_PREP(RTL8367C_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) | + FIELD_PREP(RTL8367C_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port) | + FIELD_PREP(RTL8367C_CPU_CTRL_TRAP_PORT_EXT_MASK, cpu->trap_port >> 3); - ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val); + ret = regmap_write(priv->map, RTL8367C_CPU_CTRL_REG, val); if (ret) return ret; return 0; } -static int rtl8365mb_switch_init(struct realtek_priv *priv) +static int rtl8367c_switch_init(struct realtek_priv *priv) { - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; int ret; int i; @@ -1755,9 +1744,9 @@ static int rtl8365mb_switch_init(struct realtek_priv *priv) } /* Common init jam */ - for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) { - ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg, - rtl8365mb_init_jam_common[i].val); + for (i = 0; i < ARRAY_SIZE(rtl8367c_init_jam_common); i++) { + ret = regmap_write(priv->map, rtl8367c_init_jam_common[i].reg, + rtl8367c_init_jam_common[i].val); if (ret) return ret; } @@ -1765,60 +1754,60 @@ static int rtl8365mb_switch_init(struct realtek_priv *priv) return 0; } -static int rtl8365mb_reset_chip(struct realtek_priv *priv) +static int rtl8367c_reset_chip(struct realtek_priv *priv) { u32 val; - priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG, - FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, + priv->write_reg_noack(priv, RTL8367C_CHIP_RESET_REG, + FIELD_PREP(RTL8367C_CHIP_RESET_HW_MASK, 1)); /* Realtek documentation says the chip needs 1 second to reset. Sleep * for 100 ms before accessing any registers to prevent ACK timeouts. */ msleep(100); - return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val, - !(val & RTL8365MB_CHIP_RESET_HW_MASK), + return regmap_read_poll_timeout(priv->map, RTL8367C_CHIP_RESET_REG, val, + !(val & RTL8367C_CHIP_RESET_HW_MASK), 20000, 1e6); } -static int rtl8365mb_setup(struct dsa_switch *ds) +static int rtl8367c_setup(struct dsa_switch *ds) { struct realtek_priv *priv = ds->priv; - struct rtl8365mb *mb; + struct rtl8367c *mb; int ret; int i; mb = priv->chip_data; - ret = rtl8365mb_reset_chip(priv); + ret = rtl8367c_reset_chip(priv); if (ret) { dev_err(priv->dev, "failed to reset chip: %d\n", ret); goto out_error; } /* Configure switch to vendor-defined initial state */ - ret = rtl8365mb_switch_init(priv); + ret = rtl8367c_switch_init(priv); if (ret) { dev_err(priv->dev, "failed to initialize switch: %d\n", ret); goto out_error; } /* Set up cascading IRQs */ - ret = rtl8365mb_irq_setup(priv); + ret = rtl8367c_irq_setup(priv); if (ret == -EPROBE_DEFER) return ret; else if (ret) dev_info(priv->dev, "no interrupt support\n"); /* Configure CPU tagging */ - ret = rtl8365mb_cpu_config(priv); + ret = rtl8367c_cpu_config(priv); if (ret) goto out_teardown_irq; /* Configure ports */ for (i = 0; i < priv->num_ports; i++) { - struct rtl8365mb_port *p = &mb->ports[i]; + struct rtl8367c_port *p = &mb->ports[i]; if (dsa_is_unused_port(priv->ds, i)) continue; @@ -1828,12 +1817,12 @@ static int rtl8365mb_setup(struct dsa_switch *ds) p->index = i; /* Forward only to the CPU */ - ret = rtl8365mb_port_set_isolation(priv, i, BIT(priv->cpu_port)); + ret = rtl8367c_port_set_isolation(priv, i, BIT(priv->cpu_port)); if (ret) goto out_teardown_irq; /* Disable learning */ - ret = rtl8365mb_port_set_learning(priv, i, false); + ret = rtl8367c_port_set_learning(priv, i, false); if (ret) goto out_teardown_irq; @@ -1841,13 +1830,13 @@ static int rtl8365mb_setup(struct dsa_switch *ds) * ports will still forward frames to the CPU despite being * administratively down by default. */ - rtl8365mb_port_stp_state_set(priv->ds, i, BR_STATE_DISABLED); + rtl8367c_port_stp_state_set(priv->ds, i, BR_STATE_DISABLED); } /* Set maximum packet length to 1536 bytes */ - ret = regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG, - RTL8365MB_CFG0_MAX_LEN_MASK, - FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK, 1536)); + ret = regmap_update_bits(priv->map, RTL8367C_CFG0_MAX_LEN_REG, + RTL8367C_CFG0_MAX_LEN_MASK, + FIELD_PREP(RTL8367C_CFG0_MAX_LEN_MASK, 1536)); if (ret) goto out_teardown_irq; @@ -1860,60 +1849,60 @@ static int rtl8365mb_setup(struct dsa_switch *ds) } /* Start statistics counter polling */ - rtl8365mb_stats_setup(priv); + rtl8367c_stats_setup(priv); return 0; out_teardown_irq: - rtl8365mb_irq_teardown(priv); + rtl8367c_irq_teardown(priv); out_error: return ret; } -static void rtl8365mb_teardown(struct dsa_switch *ds) +static void rtl8367c_teardown(struct dsa_switch *ds) { struct realtek_priv *priv = ds->priv; - rtl8365mb_stats_teardown(priv); - rtl8365mb_irq_teardown(priv); + rtl8367c_stats_teardown(priv); + rtl8367c_irq_teardown(priv); } -static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver) +static int rtl8367c_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver) { int ret; /* For some reason we have to write a magic value to an arbitrary * register whenever accessing the chip ID/version registers. */ - ret = regmap_write(map, RTL8365MB_MAGIC_REG, RTL8365MB_MAGIC_VALUE); + ret = regmap_write(map, RTL8367C_MAGIC_REG, RTL8367C_MAGIC_VALUE); if (ret) return ret; - ret = regmap_read(map, RTL8365MB_CHIP_ID_REG, id); + ret = regmap_read(map, RTL8367C_CHIP_ID_REG, id); if (ret) return ret; - ret = regmap_read(map, RTL8365MB_CHIP_VER_REG, ver); + ret = regmap_read(map, RTL8367C_CHIP_VER_REG, ver); if (ret) return ret; /* Reset magic register */ - ret = regmap_write(map, RTL8365MB_MAGIC_REG, 0); + ret = regmap_write(map, RTL8367C_MAGIC_REG, 0); if (ret) return ret; return 0; } -static int rtl8365mb_detect(struct realtek_priv *priv) +static int rtl8367c_detect(struct realtek_priv *priv) { - struct rtl8365mb *mb = priv->chip_data; + struct rtl8367c *mb = priv->chip_data; u32 chip_id; u32 chip_ver; int ret; - ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver); + ret = rtl8367c_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver); if (ret) { dev_err(priv->dev, "failed to read chip id and version: %d\n", ret); @@ -1921,29 +1910,29 @@ static int rtl8365mb_detect(struct realtek_priv *priv) } switch (chip_id) { - case RTL8365MB_CHIP_ID_8365MB_VC: + case RTL8367C_CHIP_ID_8365MB_VC: dev_info(priv->dev, - "found an RTL8365MB-VC switch (ver=0x%04x)\n", - chip_ver); + "found an RTL8365MB-VC switch (ver=0x%04x)\n", + chip_ver); - priv->cpu_port = RTL8365MB_CPU_PORT_NUM_8365MB_VC; + priv->cpu_port = RTL8367C_CPU_PORT_NUM_8365MB_VC; priv->num_ports = priv->cpu_port + 1; mb->priv = priv; mb->chip_id = chip_id; mb->chip_ver = chip_ver; mb->port_mask = BIT(priv->num_ports) - 1; - mb->learn_limit_max = RTL8365MB_LEARN_LIMIT_MAX_8365MB_VC; - mb->jam_table = rtl8365mb_init_jam_8365mb_vc; - mb->jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc); + mb->learn_limit_max = RTL8367C_LEARN_LIMIT_MAX; + mb->jam_table = rtl8367c_init_jam_8367c; + mb->jam_size = ARRAY_SIZE(rtl8367c_init_jam_8367c); mb->cpu.enable = 1; mb->cpu.mask = BIT(priv->cpu_port); mb->cpu.trap_port = priv->cpu_port; - mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL; - mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA; - mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES; - mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES; + mb->cpu.insert = RTL8367C_CPU_INSERT_TO_ALL; + mb->cpu.position = RTL8367C_CPU_POS_AFTER_SA; + mb->cpu.rx_length = RTL8367C_CPU_RXLEN_64BYTES; + mb->cpu.format = RTL8367C_CPU_FORMAT_8BYTES; break; default: @@ -1956,38 +1945,38 @@ static int rtl8365mb_detect(struct realtek_priv *priv) return 0; } -static const struct dsa_switch_ops rtl8365mb_switch_ops = { - .get_tag_protocol = rtl8365mb_get_tag_protocol, - .setup = rtl8365mb_setup, - .teardown = rtl8365mb_teardown, - .phy_read = rtl8365mb_phy_read, - .phy_write = rtl8365mb_phy_write, - .phylink_validate = rtl8365mb_phylink_validate, - .phylink_mac_config = rtl8365mb_phylink_mac_config, - .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down, - .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up, - .port_stp_state_set = rtl8365mb_port_stp_state_set, - .get_strings = rtl8365mb_get_strings, - .get_ethtool_stats = rtl8365mb_get_ethtool_stats, - .get_sset_count = rtl8365mb_get_sset_count, - .get_eth_phy_stats = rtl8365mb_get_phy_stats, - .get_eth_mac_stats = rtl8365mb_get_mac_stats, - .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats, - .get_stats64 = rtl8365mb_get_stats64, +static const struct dsa_switch_ops rtl8367c_switch_ops = { + .get_tag_protocol = rtl8367c_get_tag_protocol, + .setup = rtl8367c_setup, + .teardown = rtl8367c_teardown, + .phy_read = rtl8367c_phy_read, + .phy_write = rtl8367c_phy_write, + .phylink_validate = rtl8367c_phylink_validate, + .phylink_mac_config = rtl8367c_phylink_mac_config, + .phylink_mac_link_down = rtl8367c_phylink_mac_link_down, + .phylink_mac_link_up = rtl8367c_phylink_mac_link_up, + .port_stp_state_set = rtl8367c_port_stp_state_set, + .get_strings = rtl8367c_get_strings, + .get_ethtool_stats = rtl8367c_get_ethtool_stats, + .get_sset_count = rtl8367c_get_sset_count, + .get_eth_phy_stats = rtl8367c_get_phy_stats, + .get_eth_mac_stats = rtl8367c_get_mac_stats, + .get_eth_ctrl_stats = rtl8367c_get_ctrl_stats, + .get_stats64 = rtl8367c_get_stats64, }; -static const struct realtek_ops rtl8365mb_ops = { - .detect = rtl8365mb_detect, +static const struct realtek_ops rtl8367c_ops = { + .detect = rtl8367c_detect, }; -const struct realtek_variant rtl8365mb_variant = { - .ds_ops = &rtl8365mb_switch_ops, - .ops = &rtl8365mb_ops, +const struct realtek_variant rtl8367c_variant = { + .ds_ops = &rtl8367c_switch_ops, + .ops = &rtl8367c_ops, .clk_delay = 10, .cmd_read = 0xb9, .cmd_write = 0xb8, - .chip_data_sz = sizeof(struct rtl8365mb), + .chip_data_sz = sizeof(struct rtl8367c), }; -EXPORT_SYMBOL_GPL(rtl8365mb_variant); +EXPORT_SYMBOL_GPL(rtl8367c_variant); MODULE_LICENSE("GPL"); diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index a5671ab896b3..4574782ae52e 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -1025,7 +1025,7 @@ static struct phy_driver realtek_drvs[] = { .write_page = rtl821x_write_page, }, { PHY_ID_MATCH_EXACT(0x001cc942), - .name = "RTL8365MB-VC Gigabit Ethernet", + .name = "RTL8367C Gigabit Ethernet", /* Interrupt handling analogous to RTL8366RB */ .config_intr = genphy_no_config_intr, .handle_interrupt = genphy_handle_interrupt_no_ack,