diff mbox series

[net-next,9/9] mlxsw: core_env: Forbid module reset on RJ45 ports

Message ID 20220126103037.234986-10-idosch@nvidia.com (mailing list archive)
State Accepted
Commit b7347cdf10fadee4c6d23cc11f03c91336e6831a
Delegated to: Netdev Maintainers
Headers show
Series mlxsw: Add RJ45 ports support | expand

Checks

Context Check Description
netdev/tree_selection success Clearly marked for net-next
netdev/apply success Patch already applied to net-next

Commit Message

Ido Schimmel Jan. 26, 2022, 10:30 a.m. UTC 
From: Danielle Ratson <danieller@nvidia.com>

Transceiver module reset through 'rst' field in PMAOS register is not
supported on RJ45 ports, so module reset should be rejected.

Therefore, before trying to access this field, validate the port module
type that was queried during initialization and return an error to user
space in case the port module type is RJ45 (twisted pair).

Output example:

 # ethtool --reset swp11 phy
 ETHTOOL_RESET 0x40
 Cannot issue ETHTOOL_RESET: Invalid argument
 $ dmesg
 mlxsw_spectrum 0000:03:00.0 swp11: Reset module is not supported on port module type

Signed-off-by: Danielle Ratson <danieller@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlxsw/core_env.c | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/ethernet/mellanox/mlxsw/core_env.c b/drivers/net/ethernet/mellanox/mlxsw/core_env.c
index b34de64a4082..4e3de2846205 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/core_env.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/core_env.c
@@ -467,6 +467,12 @@  int mlxsw_env_reset_module(struct net_device *netdev,
 
 	mutex_lock(&mlxsw_env->module_info_lock);
 
+	err = __mlxsw_env_validate_module_type(mlxsw_core, module);
+	if (err) {
+		netdev_err(netdev, "Reset module is not supported on port module type\n");
+		goto out;
+	}
+
 	if (mlxsw_env->module_info[module].num_ports_up) {
 		netdev_err(netdev, "Cannot reset module when ports using it are administratively up\n");
 		err = -EINVAL;