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[187.49.235.234]) by smtp.gmail.com with ESMTPSA id n9sm6899945otf.9.2022.02.09.13.14.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Feb 2022 13:14:15 -0800 (PST) From: Luiz Angelo Daros de Luca To: netdev@vger.kernel.org Cc: linus.walleij@linaro.org, andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, davem@davemloft.net, kuba@kernel.org, alsi@bang-olufsen.dk, arinc.unal@arinc9.com, Luiz Angelo Daros de Luca Subject: [PATCH net-next 2/2] net: dsa: realtek: rtl8365mb: add support for rtl8_4t Date: Wed, 9 Feb 2022 18:13:12 -0300 Message-Id: <20220209211312.7242-3-luizluca@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220209211312.7242-1-luizluca@gmail.com> References: <20220209211312.7242-1-luizluca@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The tailing tag is also supported by this family. The default is still rtl8_4 but now the switch supports changing the tag to rtl8_4t. Signed-off-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/rtl8365mb.c | 63 +++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c index e0c7f64bc56f..02d1521887ae 100644 --- a/drivers/net/dsa/realtek/rtl8365mb.c +++ b/drivers/net/dsa/realtek/rtl8365mb.c @@ -853,9 +853,70 @@ static enum dsa_tag_protocol rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port, enum dsa_tag_protocol mp) { + struct realtek_priv *priv = ds->priv; + u32 val; + + /* No way to return error */ + regmap_read(priv->map, RTL8365MB_CPU_CTRL_REG, &val); + + switch (FIELD_GET(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, val)) { + case RTL8365MB_CPU_FORMAT_4BYTES: + /* Similar to DSA_TAG_PROTO_RTL4_A but with 1-byte version + * To CPU: [0x88 0x99 0x04 portnum]. Not supported yet. + */ + break; + case RTL8365MB_CPU_FORMAT_8BYTES: + switch (FIELD_GET(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, val)) { + case RTL8365MB_CPU_POS_BEFORE_CRC: + return DSA_TAG_PROTO_RTL8_4T; + case RTL8365MB_CPU_POS_AFTER_SA: + default: + return DSA_TAG_PROTO_RTL8_4; + } + break; + } + return DSA_TAG_PROTO_RTL8_4; } +static int rtl8365mb_change_tag_protocol(struct dsa_switch *ds, int cpu, + enum dsa_tag_protocol proto) +{ + struct realtek_priv *priv = ds->priv; + int tag_position; + int tag_format; + int ret; + + switch (proto) { + case DSA_TAG_PROTO_RTL8_4: + tag_format = RTL8365MB_CPU_FORMAT_8BYTES; + tag_position = RTL8365MB_CPU_POS_AFTER_SA; + break; + case DSA_TAG_PROTO_RTL8_4T: + tag_format = RTL8365MB_CPU_FORMAT_8BYTES; + tag_position = RTL8365MB_CPU_POS_BEFORE_CRC; + break; + /* The switch also supports a 4-byte format, similar to rtl4a but with + * the same 0x04 8-bit version and probably 8-bit port source/dest. + * There is no public doc about it. Not supported yet. + */ + default: + return -EPROTONOSUPPORT; + } + + ret = regmap_update_bits(priv->map, RTL8365MB_CPU_CTRL_REG, + RTL8365MB_CPU_CTRL_TAG_POSITION_MASK | + RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, + FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, + tag_position) | + FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, + tag_format)); + if (ret) + return ret; + + return 0; +} + static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, phy_interface_t interface) { @@ -2079,6 +2140,7 @@ static int rtl8365mb_detect(struct realtek_priv *priv) static const struct dsa_switch_ops rtl8365mb_switch_ops_smi = { .get_tag_protocol = rtl8365mb_get_tag_protocol, + .change_tag_protocol = rtl8365mb_change_tag_protocol, .setup = rtl8365mb_setup, .teardown = rtl8365mb_teardown, .phylink_get_caps = rtl8365mb_phylink_get_caps, @@ -2097,6 +2159,7 @@ static const struct dsa_switch_ops rtl8365mb_switch_ops_smi = { static const struct dsa_switch_ops rtl8365mb_switch_ops_mdio = { .get_tag_protocol = rtl8365mb_get_tag_protocol, + .change_tag_protocol = rtl8365mb_change_tag_protocol, .setup = rtl8365mb_setup, .teardown = rtl8365mb_teardown, .phylink_get_caps = rtl8365mb_phylink_get_caps,